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HDTV ATSC-8VSB chip design can be tested

Author: HuHaiBo
Tutor: ChenZhongJing
School: Zhejiang University
Course: Microelectronics and Solid State Electronics
Keywords: DSM DFT SAF scan chain
CLC: TN948
Type: Master's thesis
Year: 2002
Downloads: 89
Quote: 0
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Abstract


One measure of product quality is the defect level. Chip test is essential for controlling the defect level. A higher test coverage means a lower defect level. Therefore, the goal of chip test is to achieve a high test coverage at an affordable cost.Scaling transistor feature size allows greater density, higher performance and lower cost. However, scaling of gate oxide thickness, source/drain extension, junction depths and gate lengths have brought about several new technology issues invalidating some earlier methods for testing ICs. Entering the DSM(deepubmicron) era, New failure mechanisms and the huge amount of design data have brought pressure to all aspects of IC design.Design for test(DFF) is an important testing technique addressing these challenges. A scanhain based DPI flow is integrated with the design flows of our ATSC?VSB chip design. ATSC?VSB is the channeleceiving chip of f-JDTV?VSB terraransmission system. We constructed scanhains of multiplexed fliplops style to achieve a SAF(stuckt fault) test coverage of 93% using 112 patterns for the chip. A boundary scan architecture is also implemented according to IEEE1149. 1 standard.

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > TV > TV and television equipment
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