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Study on Implementation of a Scalable Length and High Speed FFT Processor Based on FPGA

Author: SunXue
Tutor: LiuXiaoMing
School: Chongqing University
Course: Circuits and Systems
Keywords: The number of combinations of fast Fourier transform Field Programmable Gate Array Memory Coordinate rotation digital computer The expansion of structures Assembly line
Type: Master's thesis
Year: 2004
Downloads: 1148
Quote: 5
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DFT (Discrete Fourier Transform) as the signal is converted from the time domain to the frequency domain of the basic operations, plays a central role in a variety of digital signal processing, and its fast algorithm FFT (Fast Fourier Transform) in a wireless communication, speech recognition, image processing and spectrum analysis and other fields have a wide range of applications. Especially with the advent of OFDM (orthogonal frequency division multiplexing) technology, the type of OFDM systems require a different transformation point FFT operation, how to more quickly, more flexible implementation of the FFT is becoming increasingly important. This paper presents FPGA (Field Programmable Gate Array)-based algorithm to achieve the Fourier Transform Points of scalable high-speed FFT processor structure design as well as various functional modules, including the high number of combinations of FFT algorithm FFT cascade pipeline work structure, inter-stage mixing sequence RAM read / write addresses the regularity and address generator design, complement code to achieve the structure of the short point FFT array processing and complement can be used to achieve different levels to complete the data phase rotation, but has the same pipeline structure CORDIC (coordinate rotation digital computer) processor; pipeline processing capabilities of high-speed FFT processor and its functional verification platform. On FPGA-based scalable high-speed FFT processor studies have shown that: (1) as field programmable IC (Integrated Circuit) technology development and applications mature, the scale and variety of devices increasing, field programmable IC design and application costs continue to lower, more and more areas and products, especially the production of small batch, update fast digital system products directly using FPGA as the representative of on-site hardware programmable IC monolithic integration has become an inevitable trend . CPLD (Complex Programmable Logic Devices) / FPGA technology is an ideal tool for rapid prototyping of the FFT algorithm. (2) for high-speed, large-capacity data stream real-time processing of the FFT, by VLSI (VLSI) the device parallel processing or multi-stage pipeline processing to achieve. In particular, the FFT structure of the multi-stage pipeline processing different points FFT calculation can be easily realized by increasing or decreasing the module series so that the completion of the FFT processor based on CPLD / FPGA device. (3) derived by the analysis and comparison of various characteristics and laws of the FFT algorithm, based on the the FPGA design Fourier transform Points scalable high-speed FFT processor, the high number of combinations of FFT algorithm is the best choice, base-X any based FFT has extended limitations, because the latter is a special case of the former, the former general rule summary can be drawn, making the structure expansion of high-speed FFT processor is more convenient and flexible. (4) In order to FPGA to achieve more optimized FFT design synthesis and layout for FPGA features, changing the algorithm of a number of functional modules, such as the realization of the twiddle factor multiplication CORDIC algorithm; adjust some of the design of the structure of the modular units, such as CORDIC iteration unit complement structure. (5) theory, a general summary of the number of combinations of FFT algorithm pipeline with read / write data between stages mixed sequence read / write the same piece of RAM RAM address Occurrence to it as a guide, the flexibility to change the structure of the FFT processor and the size of the Fourier transform of the data, this junction Chongqing University Thesis structure replaced the completion of the two RAM data mixed sequence of ping-pong structure that does not involve memory read and write The switch control logic is very simple, and the consumption of memory resources to save half. (6) According to the experimental results of the high-speed FFT processor design structure with pipeline processing capabilities using FPGA: clock operates at 40MHz, the input data rate of 20MHz, calculated 1024 16-bit word length fixed-point FFT computation can be achieved 52us order of magnitude (measured results). It showed the correct high-speed performance of the design of the structure can be achieved to meet the real-time processing algorithm theoretical analysis based on FFT processor FPGA implementation of the functional modules involved.

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