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Design of Finite Field Polynomail Multiplier

Author: HanFang
Tutor: LaiZongSheng
School: East China Normal University
Course: Microelectronics and Solid State Electronics
Keywords: Finite field Fast algorithm Polynomial multiplication FNT Modular multiplication
CLC: TN918
Type: Master's thesis
Year: 2005
Downloads: 138
Quote: 0
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Abstract


Multiplying on the finite field is a primitive operation of many cryptographic systems and coding theory. Finite field multiplication efficiency largely determines the performance of the entire system. The speed of operation is essential for many cryptosystems, in some password system, its main computation from the calculation of the finite field integer coefficients polynomials. Thereby increasing finite field integer coefficients polynomial multiplication speed is useful for this kind of password system application value. In this paper, based on the number-theoretic transform algorithm structure completed fast polynomial multiplication of finite field arithmetic core design and FPGA implementation and test validation, including the FBI from algorithm design, system architecture design, module design and implementation of the various sub-system simulation to download of FPGA implementation and testing of the entire process. A study design with independent intellectual property rights of high-speed, high-precision finite field polynomial multiplication nuclear. A viable hardware implementation structure, with error-free, fast, and low design complexity. 1,000,000 Xilinx's Virtex II devices, two 256-point finite field of polynomial multiplication only 65 4μs. 2-fold improvement compared to the speed and a 3 PC parallel processing software method; 7-fold improvement compared to the speed processing and the use of a PC. Can be directly applied to the digital signature operation. This article features the main work is as follows: 1, circular convolution using Fermat number transform (FNT) properties of integer coefficients polynomial multiplication, improve the accuracy and speed of operation. Use iteration and polynomial split multiplication skills, the higher powers of polynomial multiplication into low power of polynomial multiplication superposition, to overcome the limit of the FNT computing points. The structure and the use of ping-pong RAM increase computing power, pipeline structure. 2, using a similar base 4 FFT fast algorithm for achieve 64 points FNT. FNT module design can be processed in parallel two sets of data. And scalable performance, parallel processing of multiple sets of data according to specific requirements. 3, the use of the new code code system for FNT operation. Which involves multiplication and modulo operation, are easily transformed into the shift operation processing subtraction is conducive to a hardware implementation. Carry modular addition and carry-save adder (MCSA) structure to improve the FNT and modular multiplication processing speed and save hardware resources. 5, the operation of nuclear Virtex II series xc2v1000-4fg256 is to achieve, the maximum operating frequency up to 100MHz, the computing time required to complete a 65 4μs. And the operation of nuclear successfully applied to the finite field polynomial exponentiation.

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