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Design and Implementation of a VLIW DSP Assembler and Code Generator

Author: ChenHuiBin
Tutor: LiuChunLin
School: National University of Defense Science and Technology
Course: Computer Science and Technology
Keywords: Assembler Code generator VLIW DSP Cluster assignment Dispatch UAS
CLC: TP332
Type: Master's thesis
Year: 2005
Downloads: 167
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Compared with traditional DSPs modern DSPs uses the more ILP techniques to improve the performance of the machine . The other hand, they exhibit a regular, and can be compiled into the system structure , and makes it possible for them to construct efficient optimizing compiler . This paper discusses such a DSP, VLIW architecture, clustering , and be able to perform multiple operations in a single clock cycle . We described this VLIW DSP assembler and the structure of the code generator . In order to facilitate handling of forward references , VLIW DSP assembler organized into twice structures . First pass only records in the source file symbol ( label ) information , the second time to rescan the source file , the use of previously collected information to generate the target file . VLIW DSP assembler features include : using lex and yacc generated lexical and syntax analyzer ; assembler statements in assembler form of internal representation ; instruction encoding information stored in the data table , the coded instructions when using a common process queries these table to determine the encoding format of the instruction opcode, and then call the appropriate encoding function to generate machine code . The VLIW DSP code generator based on the framework of the IMPACT C compiler . For VLIW DSP custom machine specifications and machine description , and the use of a the IMPACT template construct its code generator . A notable feature of the VLIW DSP architecture is divided into clusters , i.e. large concentration of the register file is divided into a plurality of blocks , each block with several functional units associated cluster . Correspondingly, with this feature , the code generation is an important step is the cluster allocation, is the mapping of each operation and its operand to the appropriate clusters . Cluster allocation should be fully utilized so that each functional unit clusters , and seek to reduce the data transfer between the clusters . We give a unified cluster allocation and scheduling algorithm (UAS) for VLIW DSP implementation , the characteristics of the algorithm is to cluster allocation and scheduling together when scheduling an operation , as well as the operation and its operands to allocate appropriate cluster .

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CLC: > Industrial Technology > Automation technology,computer technology > Computing technology,computer technology > Electronic digital computer (not a continuous role in computer ) > Arithmetic unit and the controller (CPU)
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