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Design and Realize the IP Core of 3D Embedded Graphics Processing Unit Based on FPGA

Author: TanXianQiang
Tutor: WuNing
School: Nanjing University of Aeronautics and Astronautics
Course: Circuits and Systems
Keywords: Graphics Processor Graphics pipeline IP core FPGA Verilog HDL
CLC: TP391.41
Type: Master's thesis
Year: 2010
Downloads: 112
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Abstract


The graphics processing system is an important part of modern computer systems , the traditional graphics processing system using a dedicated graphics processor GPU to alleviate the burden on the CPU in the graphics processing , and the graphical display of many electronic products With regard demand continuously improve slightly inferior performance embedded systems require a dedicated GPU to handle more and more complex graphics . Traditional graphics processor GPU development has been relatively mature , and research for embedded systems , high-performance GPU , but there are many issues to be resolved . Therefore, with regard to the the embedded GPU design and research of great significance . Based on in-depth understanding of computer graphics and related algorithms , the paper reviews the history of the development of the graphics processor and its rendering mechanism , the composition of the graphics system . Papers using the OpenGL graphics API selected 21 basic API commands defined rendering list format and command word encoding and IP core design as the Statute . Geometry and raster graphics pipeline is divided into two parts , eventually refined into eight modules , respectively, be achieved with four FPGA Verilog language . GPU module papers on a detailed analysis and design , focus on geometric transformation module scaling transformation and combinations transform light module for the processing of the two light sources , as well as the triangle primitives reject shear and anti- aliasing . IP core design , create, debug , and comprehensive simulation in Quartus II 6.0 integrated development environment following IP -core working frequency of 50MHz FPGA logic resources occupancy rate of about 80% in the total of occupied logic unit 60000 LE . Final verification platform can execute correctly selected 21 API commands , and completion of the three-dimensional objects , pan, zoom , lighting calculations , excluding shear and rasterization .

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CLC: > Industrial Technology > Automation technology,computer technology > Computing technology,computer technology > Computer applications > Information processing (information processing) > Pattern Recognition and devices > Image recognition device
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