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Realization and Verification of IP Core of SPI Protocol Based on AMBA Bus

Author: ZhaoJie
Tutor: YiBo
School: University of Science and Technology of China
Course: Microelectronics and Solid State Electronics
Keywords: SOC IP core AMBA bus SPI protocol Verilog HDL FPGA
CLC: TN47
Type: Master's thesis
Year: 2009
Downloads: 194
Quote: 5
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Abstract


Nowdays as the SOC design is getting more and more complicated, two major challenges to its development is the multiplexing and interconnect of IP core. SPI is a high-speed, full-duplex, synchronous communication bus, and its simple connection could save PCB space. More and more IC chips are realizinig this protocol. We designed an IP core of SPI protocol, which could be configured as SPI Master or SPI Slave, could set different transmission speed, and could work in any one of the four clock modes. This is very significant and is in line with the development of SOC design technology.Proposed a comprehensive analysis comparing Silicore’s Wishbone, IBM’s CoreConnect and ARM’s AMBA bus technical characteristics. The bus configuration of Wishbone is simple, flexible, and has much free resources. CoreConnect bus structure is integral, common and powerful, but it is too comlicated for embedded applications. AMBA bus has many third-parties support, and has become one of the standards of the existing interconnection bus. Especially, the APB bus which applies to low-speed connection has a simple structre, low-power, and practicability. It has a wide application prospects.According to Top-Down design theory, I described the method to design the SPI IP core module based on AMBA bus. Analyzed the design objectives, and defined the input and output signal of the module. Then further divided its sub-modules and analyzed its internal signals, and present a complete module and signal connection diagram as well as detailed registers settings. Afterwards, described the realization of the IP-core using Verilog HDL. Described the design concept, and then introduced the design process of several important modules such as Clock Prescaler, APB interface and Transmit/Receive Logic, and then discussed typical problems in the design process and its solution.Executed Function Simulation and FPGA Timing Simulation of the IP core using mainstream simulation software Modelsim and QuartusII. Tested the reset process,and checked the data transmission under different Clock speed and under all four clock modes. All the registers value and read/write data are in line with the data expected. Passed the simulation process successfully.

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Microelectronics, integrated circuit (IC) > LSI,ultra LSI
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