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ASIC Implementation of Multilevel Filter Algorithm for Small Targets of Infrared Images Detection
Author: SunJianWei
Tutor: ChenChaoYang
School: Huazhong University of Science and Technology
Course: Pattern Recognition and Intelligent Systems
Keywords: Multi-stage filter Application specific integrated circuit Small Target Detection Can be integrated design Static timing analysis
CLC: TP274.52
Type: Master's thesis
Year: 2005
Downloads: 138
Quote: 0
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Abstract
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Multi-level filtering algorithm for infrared image small target detection by changing the basic filter template series , different bandwidth filter templates , the ability to achieve simultaneous detection of different sizes small targets . Detailed discussion of multi-level filtering algorithm based on the overall structure of the multi-level filtering algorithm . External system requirements , multi-stage filter design requirements and typical applications of the chip , and discusses in detail the the architecture internal implementation mechanism . 1 × 3 filter template, 1 × 5 and 1 × 7 cascade form the filter templates ; multi-resolution Gaussian pyramid processing algorithm can handle larger target , while the first stage processing stage can effectively weaken the goals and noise ; data path consists of three parallel data channels , and corresponding to the detection of 3 × 3,5 × 5 and 7 × 7 three small target ; each data channel employs a pipelined architecture , circuit multiplication by shift and add circuit configuration to improve the computing speed ; using fixed-point arithmetic , calculation accuracy of the 8 - bit binary fraction can handle 8-16 wide data . This article focuses on the implementation of the data path ; start the detailed discussion focusing on improving the accuracy problems and propose solutions ; describe in detail the FIFO state machine and the state of the input and output signals . Register transfer level design methodology -oriented integrated to complete the circuit design ; through functional simulation , and a detailed error analysis ; logic synthesis about the process involved in the comprehensive concept of environment settings , constraint set ; static timing analysis and comparison two different stages of the STA ; brief introduction to the basic physical design process , especially for the allocation problems that involve multiple clock network effective solutions . Relates to a multi-stage filter chip indicators : Throughput 5M-10M pixels / sec ; clocked at 50MHz ; support the format of the image data of 128 × 128 / 256 × 256 / 320 × 240 three frames .
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CLC: > Industrial Technology > Automation technology,computer technology > Automation technology and equipment > Automation systems > Data processing, data processing system > Automatic detection system using a variety of new technologies > Infrared detector and its equipment
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