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Hierarchical Model Checking Study on Microprocessor Verification

Author: WangDi
Tutor: WuWeiMin
School: Tsinghua University
Course: Computer Science and Technology
Keywords: model checking hierarchical verification microprocessor ICCAD
CLC: TP332
Type: Master's thesis
Year: 2005
Downloads: 138
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Abstract


Verification has become one of the most important and critical problemsin ICCAD area today. Model checking tools have been used for years inverifying finite-state concurrent systems. However, by flattening out thebehavior of a target system before verification, inherent modularities, eitherfunctional or structural, are not exploited by these tools and methodologies.So it becomes hard to address whole complex designs such as amicroprocessor. In this work, targeting at microprocessor verification, we firstexploit the modular character of RTL specification and build formal modelsbottom-up in a hierarchical way. Second, by imposing additional constraintsto model checking process via inter-modular invariants, state space can begreatly reduced and reflect more accurately about system behavior byeliminating those unreachable states. We integrate our approach into NuSMVmodel checking tool and apply it to several single-issue DLX pipe-line CPUdesigns. CTL property checking results demonstrate the feasibility and showextremely large reduction both in execution time and memory consumption.

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CLC: > Industrial Technology > Automation technology,computer technology > Computing technology,computer technology > Electronic digital computer (not a continuous role in computer ) > Arithmetic unit and the controller (CPU)
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