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Research and Design of Architecture and Central Control Module in Multi-standard Video Post Processing Chip

Author: ShiChao
Tutor: YaoSuYing
School: Tianjin University
Course: Microelectronics and Solid State Electronics
Keywords: Multi-system Analog video front - end Low-power state machine Field Programmable Gate Array
CLC: TN402
Type: Master's thesis
Year: 2010
Downloads: 21
Quote: 0
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Abstract


Multi-format video display processing chips for computers and high-definition display device design and development, the main function of the computer to complete the standard format conversion between the timing as well as high-definition standard timing. The chip includes the analog front end (AFE), the main control module, non-linear scaling, skin color enhanced joint realization of several core unit. The multi-standard video display processing chip can be applied to a variety of environments, for example, can be used as a display device using a chip, the digital high-definition television display chips, a cathode ray tube and projection device display chip, a plasma display using chips, etc. to the LCD display. This paper describes a study theory and design process and verify the results of the low power consumption of the chip architecture, pattern recognition module, pixel clock generation module module. Wherein the AFE comprises a pattern recognition module, and the pixel clock generating module. The main function of the pattern recognition is to identify the standard of the input video signal, but because the input signal may occur, such as interference and noise on the signal integrity issues, and may also be metastable, if these signals directly to the identification The error may cause pixel clock generation, scaling factor calculation errors, and therefore must be added to a variety of correction function in the design of the module. The main function of the clock generation module is generated pixel clock frequency of the line synchronizing signal phase with the input video to the dynamic change, and the user can configure the phase of the pixel clock, and to require pixel clock and input pixel relative alignment, i.e. in the user configuration phase After a whole pixel clock with the original phase remains constant. The master module is the core control part of the multi-standard video display processing chip, the use of a low-power design thinking, and control of analog video front-end from the device, I2C, scaling module lookup table module, the output timing control module and color enhanced module data interaction, and as a the arbiter controller chip internal bus arbitration to prevent bus conflicts. Chip bus simplified the Wishbone agreement, in the design, due to the large number of video data and high frequency clock cycle, Wishbone interface design difficulty lies in the speed of the circuit. This paper first discusses the theoretical basis for the design of each module, and then used to top-down design approach, more specific structural division and design of the various sub-modules. According to the division of the module completed writing RTL code, and finally implemented in FPGA development board.

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Microelectronics, integrated circuit (IC) > General issues > Design
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