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Microelectronic technology after large-scale ( LSI ) , the ultra-large-scale ( VLSI ) and ultra large scale ( ULSI ) integrated era , in 1995 , into the very large scale integration ( GSI ) era . As a representative of the high-tech , integrated circuit technology has played an invaluable role in the development of the world economy . Application specific integrated circuit ( ASIC ) with a short development cycle, the development of low cost , high reliability , but also by the rapid development . Among them, the excellent performance of the cell libraries have become indispensable bridge connection between the the ASIC user and process line . Practice has proved that no good cell library it is impossible to carry out high - level ASIC design . But even in this case , an increasingly large cell libraries VLSI design to product , shortening a bottleneck to enter the market cycle . In recent years, in VLSI standard cell - based design has become a mainstream design style . But standard cell libraries become larger and larger , some as many as more than 500 . This means that to establish , validate, and maintain these standard cell library requires a lot of time, manpower and material resources , but also can not be avoided , the error will often penetrate into the cell design and the process of unit characteristics . Check this , you need to update more practical technology for a cell library regular and effective maintenance . In response to these problems , this paper focuses on the type of library in 0.35um standard cell library construction process and standard cell library , including the symbol library , layout library , library , simulation library , timing library version Gallery . In these cell library , a total of 420 units . Cell types, including types of basic units , I / O unit types , analog macrocell having various scale of SRAM , ROM macro unit . The entire process of building a database , through the application of Candece Synopsys design tools , focus on resolving the built version of the library , improved building a database technology can be more scientific and reasonable , practical , in order to optimize the height of the standard cells and standard cell width, and the wiring optimization , to achieve the purpose of the chip area is reduced .
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