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Degradation of Amorphous Silicon Thin Film Transistors under Gate and Drain Voltage Bias Stress

Author: ZhouDaPeng
Tutor: WangMingXiang
School: Suzhou University
Course: Microelectronics and Solid State Electronics
Keywords: Amorphous silicon A thin film transistor Reliability Polysilicon Scan Stress
CLC: TN321.5
Type: Master's thesis
Year: 2011
Downloads: 25
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Abstract


This paper studies the amorphous silicon thin film transistor (a-Si TFT) in gate leakage degradation under stress conditions characteristic, and to analyze the corresponding degradation mechanisms. The positive gate voltage (V g ) stress, the generation of defect states (state creation) or electron capture (electron trapping) cause the device threshold voltage (V th ) Forward drift. And degradation satisfy the relation: ΔV th = C? V g γ? Tβ, where γ ≈ 1. 5, β ≈ 0.34. And when the stress V g is negative, state creation and hole trapping (hole trapping) the combined effect of the device characteristics. DC negative V g stress, state creation basically dominated, leading to V th positive shift occurred. But when the stress voltage is high? 80V, the device is in the hole trapping mechanisms under the influence of a two-stage degradation characteristics, that is, in a period of positive V th Drift after drift took place in reverse . In the exchange of negative V g under stress, these two mechanisms depends on the dominant frequency and time stress and other factors. Therefore, we observed the opposite of another two-stage degradation. In addition, stress temperature and magnitude of these two mechanisms are enhanced. Further, these two mechanisms, and linked to the recovery phenomenon is also observed respectively. State creation and hole injection (hole injection) mechanisms, respectively, resulted in leakage current at low negative V g stress decreased, while in the high frequency negative V g stress rises. Secondly, we have studied the device in a fixed negative V g , different drain voltage (Vd) degradation behavior under stress. We found that in the DC Vd stress, state creation in V g d (= V g Vd) is negative and large dominant, while electron trapping in the positive V gd is dominant. In exchange Vd stress, state creation, electron trapping and hole trapping three mechanisms together. Stress depending on who the dominant time, frequency, V g d the other negative. In addition, the paper also discovered and studied the n-type low-temperature polysilicon TFT, the output characteristic measurement device brings degradation. To facilitate the study, we introduce V d triangular pulses to the analog output characterization behavior. We found that degradation mechanisms and DC hot-carrier effects related. Finally, we have optimized the output characteristic curve of the measurement conditions, and effectively reduce the impact of the device obtained based on the output characteristic curve accurate.

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Semiconductor technology > Semiconductor transistor ( transistor ) > Transistor: according to the process > Thin-film transistor
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