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Mbist Diagnosis Algorithm and Self-Repair

Author: RenAiLing
Tutor: LuShengLi
School: Southeast University
Course: Microelectronics and Solid State Electronics
Keywords: Embedded memory Built- in self-test Test algorithm MARCH_TB algorithm Fault model
CLC: TN407
Type: Master's thesis
Year: 2005
Downloads: 228
Quote: 6
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Abstract


Traditional automatic test equipment (ATE) has been unable to meet the demand for LSI test chip built-in self test (BIST) has been gradually applied to the chip test. System-on-chip (SOC) microelectronic applications proliferation of large embedded memory built-in self test also become necessary because, in contrast, embedded memory chip pin difficult to access, then the internal test is more effective. And stand-alone memory as embedded memory, there are generated during the production of random physical failures, which will reduce the yield of production, resulting in increased costs. Therefore, effective fault model, effective testing algorithm and its implementation is embedded memory built-in self-test design of the key issues. In response to this situation, this paper embedded memory built-in self-test technology is the core problem - test algorithm is studied, and the other memory test methods are introduced and compared. This algorithm based on the original test was carried out on the amendments put forward a higher fault coverage, and has a better ability to test fault diagnosis algorithm - MARCH TB algorithm, through independent research and development Garfield4 chip experiment shows that it achieves high fault coverage in the premise of improving the ability of fault diagnosis. For address decoding failure (AF), transmission failure (TF), stuck a t fault (SAF), coupling faults (CF), data retention fault (DRF) of these major memory fault coverage 100%, in addition to stuck a t 1 failures and transmission failures by the 1-0 transition fault, other faults can diagnose the fault types, especially to solve the stuck < sub> a t 0 failures and transmission failures by the 0-1 transition fault state coupling with low a decision to High 0 Low 0 High a decision, decided the high one with low 0 Low High 0 1 decided to diagnose the problem, because the correction algorithm makes the test time compared to the original Garfield4 in MARCH C-(2.1 ms) increase of 3 milliseconds (time data are referring to is divided into four 20K's eSRAM At the same time the test of time), but for Garfield4, since the original MARCH LR, MATS, MARCH C-MARCH TB instead of the three algorithms, so the total test time is reduced by 2 msec (as defined above) or so. This paper is organized as follows, first theoretical background, the embedded memory test and built-in self-test of the basic principles. Then the fault coverage higher MARCH C-BIST algorithm proposed an improved MARCH T B algorithm and test structures. Followed by experiments and conclusions. Finally, a summary of this article, and built-in self-test, and the prospects for future work.

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Microelectronics, integrated circuit (IC) > General issues > Testing and inspection
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