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Design and Optimization of Core Achitecture in the Many-Core Processor

Author: LiuYuPing
Tutor: GuoShuXu
School: Jilin University
Course: Circuits and Systems
Keywords: many-core forward logic Unaligned memory access Synchronization lock manager Complex Verification
CLC: TP332
Type: Master's thesis
Year: 2008
Downloads: 98
Quote: 0
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Abstract


Single- processor performance improvement in terms of frequency , structure , power consumption have encountered significant obstacles , increased parallelism is the basic method to improve processor performance , the emergence of multi-core processors is the inevitable result . With the improvement of the level of technology , the processor scale increases the processor 's power consumption is also significantly increase the power efficiency has also become one of the criteria of evaluation of processor performance . Public or multi-core architecture processor design the mononuclear complexity of the problem is one aspect of the design to be considered . Using traditional instruction-level parallelism technology organization emittance wider superscalar architecture , the increased parallelism and aggressive instruction and data prediction , data associated with dynamic scheduling algorithm , making the single-core area increase , the reduction in the efficiency of the single transistor can only increased performance and performance within a single application can easily reach the limit . Therefore , in this paper the design considerations to play the role of a single transistor to the largest initial monocyte used sequence single emitter eight water static branch prediction method . Data pipeline , blocking pipeline . After a performance test point instructions of the IPC is about 0.3, the efficiency is lower . Add FORWARD logic for this situation, in the structure , the IPC to 0.5 . FORWARD logic RTL code to optimize the delay , to meet the design requirements . Directional technology for floating-point unit added to improve the overall performance of the small nucleus . And extension of the performance of the processor , increased unaligned memory access instructions . Two similar MIPS instruction in small nuclear atomic instruction LL / SC to solve the problem of synchronization between nuclear . Finally, verification platform structures , based on the two simulator validation of the results , to ensure the accuracy and usefulness of the processor design .

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CLC: > Industrial Technology > Automation technology,computer technology > Computing technology,computer technology > Electronic digital computer (not a continuous role in computer ) > Arithmetic unit and the controller (CPU)
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