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Vertical Breakdown Theory and New Strucutres of SOI Lateral High Voltage Device

Author: HuShengDong
Tutor: LiZhaoJi
School: University of Electronic Science and Technology
Course: Microelectronics and Solid State Electronics
Keywords: ENDIF SOI Breakdown Voltage Silicon critical field Interfacial charge Media field
CLC: TN386
Type: PhD thesis
Year: 2010
Downloads: 204
Quote: 1
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Abstract

SOI (Silicon On Insulator) that \advantages, give full play to the potential of the silicon integrated circuit technology, especially SOI high-voltage integrated circuits (High Voltage Integrated Circuit, HVIC) has a special role in the field of air and space radiation resistance in the future, and thus can be widely development and application. SOI lateral high-voltage device as a of HVIC the cornerstone vertical pressure to be borne only by the top silicon and dielectric layer dielectric layer to prevent the expansion of the depletion region to the substrate layer, making conventional devices. Isolation and cooling limit, the top silicon layer and the dielectric layer is not too thick, charge Gauss theorem by both at the interface, so that the device breakdown when the dielectric layer of the electric field only the silicon critical field 3 times i.e. 100V/μm far from reach the actual common dielectric material such as SiO2 the critical field 600V/μm of SOI lateral high-voltage devices lower vertical pressure, limit of the HVIC the application and development into new applications yet to break through 600V bottleneck. In this regard, many domestic and foreign scholars have conducted in-depth research, the current work focuses on two areas of new theoretical models and new device structures. In this paper, on the basis of conventional SOI lateral high voltage devices research, around longitudinally the Withstand new theory, the study of the structure of the new model and the new devices. Perfect a uniform vertical pressure theory - media field Enhanced (ENhanced DIelectric layer Field, ENDIF) general theory; electric field for the first time to establish a new model - silicon critical threshold-based energy classic avalanche breakdown theory breakdown electric field and its thickness of the quantitative relationship model; the ENIDF under the guidance of the new structure of the two types of charge SOI high voltage device - charge Island high-pressure devices and composite media buried layer of high-pressure devices. First, to improve the media field Enhanced ENDIF theory, is to optimize the design of SOI lateral high voltage devices vertical pressure Pervasive theory. The theory is based on the critical thought of the media field, through the enhancement of the dielectric layer farms raise SOI devices vertical breakdown voltage. The interfacial charge Gauss theorem, ENDIF given three kinds of technology to enhance the electric field of the dielectric layer: ultra-thin top silicon layer with variable high critical electric field; introduction of low dielectric constant media buried layer; introduction of the charge in the dielectric layer interface. With ENDIF theoretical generalization and interpretation of the existing structure of a typical vertical pressure and for the guidance of the new device structure design. The ENDIF theory is a new high-voltage SOI device breakdown voltage terminal theory, it broke through the limitations of conventional SOI lateral high voltage devices. Second, for the first time to establish a quantitative relationship between analytical model of the silicon critical electric field and its thickness. Ionization rate formula, for the first time based on the threshold energy, the classic avalanche breakdown theory selection count and threshold energy deduced for thick, thin silicon layer of a silicon critical electric field to its thickness, as well as suitable for high, low-doped silicon critical electric field and its doped The Miscellaneous concentration of new quantitative relationship model obtained in the case of ultra-thin silicon layer or a high concentration silicon critical electric field is much higher than the conventional 30V/μm medium field of SOI high voltage device with vertical pressure unified analytical model and obtain . Critical field ionization rate relaxation discuss nanoscale ultra-thin silicon layer semi-classical model. Finally, to promote the research methods used in other semiconductor materials and devices. Third, ENDIF under the guidance of two types of charge new media field to enhance the high-pressure devices - with a the interfacial charge Island series of high-pressure devices and composite buried layer SOI high voltage device. 1) with a series of high-pressure devices Island interfacial charge (Charge Islands, CI). These devices interface on the dielectric layer to inject a high concentration doping region and is not depleted of ionized impurities of the highly doped region Coulomb force and the combined effect of the electric field force bound charges at the interface, using the interfacial charge enhancing effect of the dielectric field and the the weakening effect of the electric field of the top silicon layer to increase the breakdown voltage. Mainly includes: (1) the interfacial charge island SOI high voltage device (CI SOI), a high voltage of 606V the top silicon layer is 5μm, 1μm dielectric layer and 60μm drift region, the media field reaches 582V/μm; (2) interfacial charge island part SOI high voltage devices (CI PSOI), solving 2D Poisson equation derivation of such a structure is vertical interface electric field analytical model, 631V high voltage, the maximum surface temperature than conventional SOI and PSOI structure to reduce 14.91K and 7.66K; (3) Improved interfacial charge island portion of the SOI high voltage device (ICI PSOI) in 80μm drift District and 20μm silicon window Withstand 663V ICI PSOI than the same size CI PSOI improve 85V, while maintaining a low self-heating effects; (4) based on the ESIMOX technology CI SOI high voltage devices, in the 2μm top silicon, 0.375μm dielectric layer and 15μm drift region 230V withstand voltage much higher than the conventional structure; the (of interfacial charge island 5) double-sided SOI high voltage device (the DCI PSOI) , a 750V breakdown voltage, higher than the same size, single-sided charge the island structure 685V and conventional SOI structure 206V. 2) compound buried layer SOI high voltage device (SOI with Composite Buried Layer, CBL SOI). Class structure of the media buried layer contains two layers of oxide layer between two layers buried oxygen filling polycrystalline two buried oxygen withstand withstand voltage, and the polysilicon interface under the charge enhanced electric field of the second buried oxide layer, thereby enhancing the the breakdown voltage. Mainly includes: (1) single-window double buried layer SOI high voltage device (SWCBL SOI), the structure of the first buried layer is opened a silicon window, to obtain a high voltage of 865V of the conventional SOI structure 232V higher than the same size; (2) double-window double buried layer SOI high voltage device (DWCBL SOI), the structure of the first layer of buried oxide layer to open two windows, and connected to the top and bottom buried oxide layer. Obtain a high voltage of 1040V The 20μm top silicon layer, 2μm first buried oxide layer, 1μm second buried oxide layer and 80μm drift region, while maintaining a high withstand voltage while having a low self-heating effects. Its Breakdown Mechanism SWCBL SOI research based on the experiment developed. The detailed design of the experimental program, 2.5μm buried oxide layer, 0.5μm second buried oxide layer and 80μm drift region developed a withstand voltage up to 761V SOI LDMOS devices breakthrough a practical SOI devices voltage not exceeding 600V bottleneck.

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