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Investigation and Implementation of Key Technologies for Radio Frequency Identification Tag IC

Author: LiuDongSheng
Tutor: ZouXueCheng
School: Huazhong University of Science and Technology
Course: Microelectronics and Solid State Electronics
Keywords: Radio frequency identification Tag chip RF analog front end Rectifier circuit Energy conversion efficiency Embedded EEPROM Low power consumption Mutual authentication
CLC: TP391.44
Type: PhD thesis
Year: 2007
Downloads: 1151
Quote: 5
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Abstract


Radio Frequency Identification (RFID, Radio Frequency Identification) is a radio frequency signal automatic target recognition and access to relevant information technology. In recent years, radio frequency identification technology trend of rapid growth in the field of supply chain, access control, public transportation systems, baggage tracking. The type of domain, the requirements for radio frequency identification system is not the same. With the gradual application of radio frequency identification technology, more and more urgent demand of its lower cost and longer recognition distance. RFID tags are mainly divided into two types of passive tags and active tags, passive tags energy emission of RF energy from the reader, active tags energy from its built-in power. Passive tags with low-cost, almost no restrictions life. This paper systematically discusses the chip design and implementation of passive tags. First, discusses the the backscattered two different working principle of a radio frequency identification system based on inductive coupling and electromagnetic wave energy and data transmission mathematical model, to support the design and verification of the radio frequency identification tag chip. Second, to obtain high conversion efficiency of RF energy in the passive RFID tag chip, low-power low-cost embedded EEPROM, security authentication key technologies research and design. The radio frequency identification system is proportional to the energy conversion efficiency of recognition distance rectifying circuit pins, the thesis of the MOS gate cross-connected rectifier, and the charge pump voltage doubler two rectifier circuit structure study, the NMOS gate cross-connected rectifier circuit energy The conversion efficiency of 34.46%, and given to improve the energy conversion efficiency and the tag antenna of the utilization of the maximum available power optimization design method of the charge pump voltage doubler. Based on the SMIC 0.35μm 2P3M embedded EEPROM process to achieve a 2K-bit EEPROM memory. The memory can work in a wide voltage range: 2.5V-5V, 3.3V typical. The method effectively reduces the static power consumption, improved by increasing the control tube with slowly varying tilt clock transient boost charge pump booster circuit power consumption, based on the voltage detected by the sense amplifier is greatly reduced the EEPROM read Consumption. In addition, on page unit decoding configuration and optimization of the structure of the power distribution circuit design effectively reduces the area of ??the chip. Typically, the read current is only 40μA, erase the peak current of 250μA quiescent operating current of 20μA, Core size 0.4mm2. One-way hash message authentication code (Hash) function to build secure method proposed lightweight RFID security mutual authentication protocol based on Universal Hash function and the Multiple Hash function Toeplitz method produces a 64-bit authentication code, the given RFID security protocol commands compatible with ISO / IEC 15693 standard, using the secure authentication protocol proposed by the tag chip at only increase the costs of the 1604 standard cell and 130μW power. At the end of the paper to achieve a high-frequency radio frequency identification tag chip and chip inductive coupling system in accordance with ISO / IEC 15693 standard RFID tags validate the model. The validation results show: the design of high-frequency tag chip is able to work in between the standard definition of the minimum magnetic field Hmin (150 mA / m) and the maximum magnetic field Hmax (5 A / m). Tag chip area of ??1.5 × 1.5mm2.

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CLC: > Industrial Technology > Automation technology,computer technology > Computing technology,computer technology > Computer applications > Information processing (information processing) > Pattern Recognition and devices > Optical pattern recognition devices
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