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Improvement for Chipping Issue of Si Chip during Assembly Process
Author: PangLing
Tutor: WangMingXiang
School: Suzhou University
Course: IC Engineering
Keywords: Si chip chipping dicing die bond risk assessment
CLC: TN305.94
Type: Master's thesis
Year: 2011
Downloads: 56
Quote: 0
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Abstract
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The chip size is getting smaller and more and more die will integrate at one piece of wafer as the miniaturization of VLSI and the cost saving of manufacturing company, all these revolution will lead the company a challenger for assembly and test process in semiconductor field.As a company, for the same assembly format, if at the point view of cost, it will not add new equipment or replace the current ones. Most companies is still using the equipments which manufactured the products of 0.18μm (180nm) technology, if they want to use these“old”equipments to produce the products of 65nm even 45nm technology, many process issues will come out, and the chipping issue which mentioned in this thesis is one of them.The thesis is mainly focus on the improvement and optimization of the manufacturing process, not like other documents which is mainly focus on the study and analysis of theory model.This thesis via the Burn-In data and the phenomenon of EFA and PFA, analysis the mechanism of chipping and compare the difference of the new and old product, confirm the root cause of chipping issue at dicing step and die bond step during assembly process.Due to the old type of dicing blade cannot fit the new narrow kerf product, and the difference of die size lead the wafer expansion parameter of die bond process is also not suitable.Base on these root causes, research, analysis and successfully import one new type of dicing blade which using at dicing step. And design some experiments to finalize the correct wafer expansion parameter of this new product at die bond process.After a period’s monitoring, these actions have been proved as effectiveness and finally reduced the chipping phenomenon.At last, at the point view of customer, take some experiments for risk assessment to assess the potential fail at customer site. Via analysis the experiment data, improve and optimize the test flow for finish goods, reduce the possible fail at customer site and the related customer complaints.
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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Semiconductor technology > General issues > The semiconductor device manufacturing process and equipment > Packaging and cooling issues
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