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An Ultra-low-power Anal IC Design Technique and Its Application to High-performance Audio ADC

Author: LuoHao
Tutor: HanYan; ZhuDaZhong
School: Zhejiang University
Course: Microelectronics and Solid State Electronics
Keywords: Low-voltage low-power IC Class-C inverter Gain-boost On-chipbias ∑△ADC
CLC: TN432
Type: PhD thesis
Year: 2012
Downloads: 189
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Abstract


To copy with the urgent demand of portable electronic products as well as the need of saving energy in large electronic systems, low-voltage low-power design has become the mainstream of future CMOS IC development. A class-C inverter is recently reported to replace traditional OTA to meet the low-power low-voltage IC design challenges. The input transistors of the inverter operate in a sub-threshold region most of the time, thereby minimizing the supply voltage and power dissipation. However, the DC-gain of a traditional class-C inverter is finite, which is not suitable for many high-precision applications, such as cascade ΣΔ ADC. Moreover, because of its push-pull structure and sub-threshold characteristics, the inverter is strongly sensitive to process and supply voltage variation, which is likely to cause performance degradation or even malfunction of its application circuits. This thesis carries out thorough and systematic research focusing on the inverter-based ultra-low-power IC design technique, optimizes traditional class-C inverter through circuit innovation, and proposes a new generation of class-C inverter. In order to prove the practicality of the new generation of class-C inverter, the thesis implements an inverter-based cascade audio ΣΔ ADC, whose specifications of power consumption and performance are satisfactory. The main work and innovations include:1. In view of the problem that the DC-gain of traditional class-C inverter is low, the thesis proposes the concept, in-depth theoretical study and design implementation of a gain-boost class-C inverter. Various specifications of the gain-boost inverter are analyzed in detail by theoretical calculation and software simulation, including DC-gain, bandwidth, power consumption, output swing, input offset, PSRR, CMRR, noise, SR and settling time; Concepts of "approximate slew", maximum SR and effective SR are proposed;"triangular approximation" and "polygonal approximation" algorithms for SR calculation are povided. Compared with traditional class C inverter, the gain-boost inverter significantly increases the DC-gain from51.7dB to75.2dB. 2. In view of the problem that traditional class-C inverter is sensitive to PVT-variations, an on-chip body bias technique for the enhancement of parametric yield is proposed, which is used to compensate for PVT-variations in analog/mixed-signal IC, especially in low-voltage low-power sub-threshold IC. Meanwhile, three body bias implementation circuits (simple type, shift type and count type) are proposed. A detailed theoretical analysis and calculation is carried out for the specifications of the three body bias circuit, including body potential adjustment range, accuracy, speed, area and power consumption. A part of the body bias circuits are layout designed and tapeout.3. Application research of a new generation of class-C inverter which is based on gain-boost technique and on-chip body bias technique. Audio EA ADC is a typical representative of mixed-signaled IC, whose analog part is mainly a EA modulator. The thesis chooses ΣΔ ADC and its inside ΣΔ modulator as application circuits, and implements a high-performance, low-power audio ΣΔ ADC as well as an ultra low-power low-voltage ΣΔ modulator based on the new generation of class-C inverter.4. Tapeout and test. The proposed inverter-based audio ΣΔ ADC chip is implemented in65nm stardard CMOS process, and achieve97-dB DR,95-dB SNR and92-dB SNDR at1.2-V supply consuming1.13mW. Compared with the OTA-based chip (without the class-C inverter) of the same batch, the measured of the inverter-based chip is optimizated from1.87pJ/step to0.93pJ/step. In addition, for the pursuit of better FOM specification, the thesis implements an ultra-low-power low-voltage EA modulator chip. The modulator chip can achieve98-dB DR,93-dB SNR and90-dB SNDR over20-KHz bandwidth at0.8-V supply consuming230μW. The measured FOM specification is comparable with the international high-level journal papers published in recent years, reaching international advanced level.

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Microelectronics, integrated circuit (IC) > Semiconductor integrated circuits ( solid state circuits ) > Field-effect type
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