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FPGA Implementation of Prediction Module for AVS Encoder

Author: XiangHongLi
Tutor: ZhangGang
School: Taiyuan University of Technology
Course: Communication and Information System
Keywords: AVS OCSB intraframe prediction interframe prediction parallel processing stream-lined technology
CLC: TN919.81
Type: Master's thesis
Year: 2012
Downloads: 65
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Abstract


AVS (Audio Video coding Standard) is the audio and video codec standard of digital TV, IPTV etc that put forward independently by China. The coding efficiency of AVS is improved by2-3times compared with the first generation of standard MPEG-2, is quite with H.264, and is more concise in implementation scheme. AVS video encoding chip is different from decoding chip which realizes the AVS program play after decompression, its complexity is much higher than decoder chip. AVS video codec can be used in the products of videophone, high definition television, IPTV, portable digital products, mobile phones, STB, high definition video player etc. From the industrial chain of AVS standard "technology-patent-standard-chip and software-the whole machine and system manufacturing-digital media operation and culture industry", we know that the codec chip is one of the most important step in the AVS industrial chain.In this paper, the study of hardware realization for AVS video codec has laid a foundation for the real-time video encoding chip and played a very active role in the development of the industrial chain. The major content and research achievements in this paper are as follows: Firstly, this paper briefly explains the video compression coding standard and the encoder’s present development situation, introduces the hardware realization platform, and analyzes the key technology of the AVS standard, which provide theory basis for the design of the real-time encoder.Secondly, combined with AVS encoding algorithm and software reference model, this paper gives out the hardware-realization architecture of encoder and in view of the complexity of the hardware implementation, a piece of one-way serial bus OCSB within the unity module access protocol UMAP is abstractly designed according to the main characteristics of the Ethernet transmission. Based on this, this paper puts forward the network topology structure of arithmetic submodule, and completes the definition and description of receipting and transmitting packet for modules in AVS class standard.Thirdly, this paper made a deep research in the hardware realization process of intra frame prediction and inter frame prediction module. On the basis of the analysis of AVS standard’s arithmetic principle about intra and inter frame prediction, states the hardware structure design for prediction module in detail, and provides the specific process of the corresponding hardware algorithm design and implementation. Intra frame prediction module is divided into three submodules, including reference sample acquisition module, the pixels prediction module and pixels reconstruction module; Inter frame prediction module includes three submodules of motion estimation (ME), motion compensation (MC) and prediction motion vector (MVP). Fourthly, this paper realizes each module with VHDL language, and optimizes the algorithm structure with stream-lined technology, parallel processing and the resource sharing, and finally presents comprehensive simulation results of each hardware module including the resources utilization, the clock frequency and the simulation test waveforms. The results show that the hardware structure of the design can meet with the real-time encoding requirements of the AVS encoder.Finally, this paper summarizes the research work and puts forward the further research and improving direction.

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Communicate > Image communication, multimedia communication > Image coding
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