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Research on Function Units Design of Video CODEC Systems

Author: ZhaoXianBo
Tutor: YuLu
School: Zhejiang University
Course: Information and Communication Engineering
Keywords: AVS Interpolation Parallel processing Pipeline design USB
CLC: TN919.8
Type: Master's thesis
Year: 2007
Downloads: 144
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Abstract

With the dramatic increase of the amount of data to bring information digitization, data compression, particularly video information codec technology has become increasingly important. Existing video compression standards, the recent video compression technology standard AVS and H. 264/AVC has higher compression efficiency, but it also brings increased implementation cost. Recent video compression standard high compression rate advantage derived from the application of a series of new video processing technology, but also makes its ASIC / FPGA implementation cost increases. The author has been involved in the project of the the AVS decoder and encoder, is responsible for interpolation, loop filter and USB communication module design and debugging. Based on these experiences, this article will be interpolated module as an example to discuss the AISC design methods. And H. 264/AVC processing of half-pixel points, and bilinear filter processing different location points of 1/4 using a 6-tap filter, AVS standard using a 4-tap filter processing to the interpolation point of the 1/2 interpolation point and 1/4, so that approach data bandwidth can be reduced by 11%, also brought a dramatic increase in processing complexity of the 1/4 interpolation points. Paper design a parallel filter processing unit structure on a different location point interpolation, the data path is clear and reduces the control complexity. In this paper, the improved filtering processing unit in order to improve the overall frequency, using the the vertical pipeline input filter and improved level 2 diagonal filter can significantly shorten the cause of the delay path. For chrominance interpolation, the paper also proposed a parallel processing architecture, multiplexed multiplier unit Multiply reference data processing of each line 2. Based on correlation analysis between the adjacent rows of the reference data, the intermediate data by multiplexing reduced, the number of beats for computing. For bi-directional reference interpolation serial processing method to add a temporary the ram's achieved at the expense of the input data storage and computing unit halved. Finally, the implementation results indicate that this is an efficient interpolation structure having a higher processing speed. Video codec system not only need video compression the relentless compression unit also needs other auxiliary functional units, such as the image input and output stream input and output, as well as off-chip data storage unit. This paper introduces a method using the EZ-USB FX2CY7C68013 video codec system and PC data USB communication stream input and output units. USB the function chip work in Asynchronous Slave FIFO mode, video compression / decompression USB communication module in the system as the external main logic. USB communication using block transfer mode, and can provide high transmission speed. Experimental results show that the performance of the USB communication unit to meet the real-time AVS codec code stream delivery.

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