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Generic the timing optimization FPGA packing algorithm

Author: Liu
Tutor: ZhaoWenQing
School: Fudan University
Course: Microelectronics and Solid State Electronics
Keywords: Field Programmable Gate Array Technology mapping Packing Versatility Timing optimization
CLC: TN791
Type: Master's thesis
Year: 2011
Downloads: 21
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Abstract

FPGA design including two major hardware structure design of the chip and its supporting software system design , software system design needs to match with the chip hardware structure . Due to the the FPGA structure of diversity , often each developed a FPGA chip and its supporting software system after re- development , which to bring greatly limits the production and research of the FPGA . Versatility is necessary for a FPGA software processes . The technology mapping is an important part in the FPGA software process , and the packing is an integral part of the technology mapping , in many cases identical to the technology mapping . As the packing process and FPGA structure are closely related, and how to make the packing algorithm can be applied to a variety of different structures of the FPGA , which is a problem to be solved . At home and abroad on the general-purpose FPGA packing algorithm method based on graph matching algorithm to ensure versatility , such as PLBMAP [ 1 ] algorithm , in the area of ??optimization and optimization of the algorithm complexity have made some breakthroughs . However, with the increasing scale FPGA timing to replace the area to become the number one factor restricting the performance of the circuit , using PLBMAP get performance is not very satisfactory. Further on the basis of the previous research , a timing optimization of general-purpose FPGA packing algorithm TDU -Pack . The algorithm common analysis of the structural features of modern mainstream FPGA logic unit , the FPGA architecture modeling approach can be applied in different FPGA structure , and thus has a wide range of adaptability . The TDU-Pack algorithm optimized timing as target , the first simple user circuit timing analysis timing information to guide the packing process , and then through the timing criticality between compute nodes . The experiments show that the algorithm can be applied to not only the academic FPGA architecture and a variety of commercially available FPGA structure , and manifested beyond the PLBMAP performance . In addition , TDU-Pack academic FPGA structure showed comparable T-VPack algorithm performance , demonstrated on a commercial FPGA structure can be compared with the performance of professional FPGA mapping algorithm . This is further in-depth research on generic FPGA packing algorithm .

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Basic electronic circuits > Digital circuits > Logic circuits
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