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Based on multi-processor dual-bus architecture design and implementation

Author: ChenXiangPeng
Tutor: ShaoFengJing
School: Qingdao University
Course: Computer Software and Theory
Keywords: sCPU-dBUS Dual bus structure System switching Performance index
CLC: TP303
Type: Master's thesis
Year: 2011
Downloads: 20
Quote: 0
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Abstract


As the Internet gradually stretched into every walk of life, network security issues are attentioned by people. Sensitive data and privacy data stolen, or credit card information exposure, login and password lost, that a computer network security also attracted people’s attention. Many experts and scholars want to solve the problem from the new perspective, not limited to the formed technological fields. sCPU-dBUS security computer architecture is designed to protect system’s security from the angle of changing computers’architecture. It has one CPU and two fast sub-buses called local-bus and network-bus. The traditional bus divides into two types, local bus and network bus. It adopts physical isolation to protect sensitive data.As people requirements more and more functions, the performance of single processor gradually can’t satisfy people’s needs, so this paper put forward a new system structure with multiprocessor and dual bus on the basis of sCPU-dBUS. It is for improving the performance of a computer system. I design and emulate this security architecture on FPGA development board-V6.Firstly this paper discussed the whole hardware design of this system structure, it detailed descript CPU-BUSs bridge, multiple processors array, clock, signal Settings. At the same time, to ensure the increase CPU array can get full use and enhance the system’s robustness. We proposed a new management of multiprocess based on the way of floating supervised technology which can greatly avoid the failture of system caused by one CPU resources to collapse. And I emulate the whole system.Second, because the new computer system structure is different with traditional embedded system structure,it has the unique hardware design-CPU-BUSs bridge, the traditional performance test doesn’t consider the unique hardware. Based on performance index of single bus embedded real-time operating system and the system-switching mechanism, we design three indicators to pick up the performance of switching mechanism and CPU-BUSs bridge, it is switch delay, system transformation and data exchange rate of the two sub-system.At last, we test the performance of switching mechanism and CPU-BUSs bridge, and the results were analyzed.

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