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Embedded block coding algorithm and its hardware architecture design studies

Author: YangZuFang
Tutor: XiongChengYi
School: Central South University for Nationalities
Course: Communication and Information System
Keywords: JPEG2000 EBCOT Bit-plane coding Adaptive arithmetic coder Hardware Structure
CLC: TP301.6
Type: Master's thesis
Year: 2009
Downloads: 22
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Abstract


JPEG2000 standard is the latest still image compression standard, by the United Nations Group of Experts on the image developed in December 2000. With the traditional JPEG image compression standard, it has superior image compression performance and high image quality, image quality with support for scalable, progressive image transmission, ROI coding and lossless / lossy compression and other powerful features, can be applied to remote sensing images, image storage, internet, web browsing and other massive data compression. However, while these advantages in bringing, JPEG2000 computing complexity is increased exponentially, in particular in EBCOT Tier-1 coding algorithm. EBCOT Tier-1 coding algorithm in the bit-plane coding and arithmetic coding are two main algorithms MQ, each contain a fairly complex operation and the bit-level control, is the JPEG2000 coding system the most important processing bottlenecks. Therefore, considering the speed, size and power requirements, high-performance bit-plane coding research and MQ arithmetic coder hardware implementation has very important significance. The main thesis work reflected in the following aspects: A new word-level order to achieve high performance and parallel encoding method and bit-plane coding VLSI Architecture. New bit-plane coding method uses predictive coding technique and parallel channel pipelining technology to effectively reduce memory access and increase the system's parallel processing capabilities, a scan can be realized via a sub-block bit samples all the coefficients of all the coding. A new word-level implementation of a parallel sequence encoding bit-plane coding structure and one high-speed multi-word parallel structure. Compare the latest design, the new word-level parallel structures in the realization of a single clock cycle to complete a coefficient encoding circumstances, can be more effective in reducing hardware costs. The new multi-word structure through the use of highly parallel high-speed parallel processing technology to complete in a single clock cycle of a stripe encoding coefficients column 4, the completion of an N × N sub-block coding coefficients only about N2 / 4 clock cycles. Theoretical analysis and experimental results show that the new implementation with high-speed data processing capabilities and good value for money, can be effectively used in low-power system design. MQ arithmetic coding algorithm for in-depth analysis, give full consideration to the advantages of parallel execution hardware, at the conclusion of previous studies, based on the MQ coding algorithm has been optimized to accommodate the hardware implementation. Based on the encoding process optimization, we designed and implemented based on four lines of MQ encoder hardware architecture. The hardware structure can be processed per clock cycle a pair of input data (CX, D), and solves two of the same clock generating bytecode stream output problems. Hardware description language used to complete the design, the use of ModelSim functional simulation, and based on Altera's FPGA devices EP2SGX90FF1508 comprehensive. The results show that the designed maximum operating frequency of the encoder 78.64MHz, occupies 528 logic cells. This design uses less hardware resources in the conditions, the better meet the needs of real-time system.

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CLC: > Industrial Technology > Automation technology,computer technology > Computing technology,computer technology > General issues > Theories, methods > Algorithm Theory
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