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Research of Pll and Design Key Blocks in GPS System

Author: JiangYuJun
Tutor: ZhouJianJun
School: Shanghai Jiaotong University
Course: Software Engineering
Keywords: GPS Phase-locked loop The PFD Charge Pump Voltage Controlled Oscillator
CLC: TN967.1
Type: Master's thesis
Year: 2008
Downloads: 71
Quote: 0
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Abstract


Global satellite positioning system (Global Positioning System, GPS) receivers have a wide range of applications in the field of civil and military , and the phase-locked loop (Phase-Locked Loop, PLL) is one of the most critical of the GPS receiver module , which provide accurate GPS receiver mixer local oscillator signal . The phase-locked loop is the most challenging in the field of analog integrated circuit design a module one . The frequency synthesizer is the wireless receiver module , PFD ( Phase -Frequency Detector PFD ) , charge pump (Charge-Pump, CP) and voltage-controlled oscillator (Voltage-Controlled Oscillator, VCO) as frequency synthesizer core circuit , its performance directly affects the performance of the whole system is the receiver design difficulties . The manufacture of large-scale digital integrated circuits commonly used CMOS process , CMOS PLL is the focus of the GPS receiver chip . Research GPS system applications PLL module design and realization of a low-power and high-performance PLL system Kam frequency phase detector , charge pump and voltage controlled oscillator . The main work of this paper are as follows : First introduced some of the background of some of the phase-locked loop ; then several structures of the GPS receiver , and select low - IF architecture as the reason of the receiver structure of this article ; final details PFD in PLL system the charge pump in the the SMIC 0.18um RFCMOS process of design process , including the determination of the indicators , the choice of the structure , the concrete realization of the circuit , the simulation results and layout as well as some of the basic theory of the voltage-controlled oscillator and noise reduction technology . Simulation results show that the PFD dead zone is reduced to 0 ; the CP charge-discharge current maximum mismatch rate is less than 0.1% , and the current absolute value of the drift rate is less than 0.6% .

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Radio navigation > Navigation systems of the various institutional > Satellite navigation system
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