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Low-voltage high-performance pipelined ADC structure Research and Implementation

Author: XieLei
Tutor: ZengXiaoYang
School: Fudan University
Course: Microelectronics and Solid State Electronics
Keywords: Low Voltage Assembly line ADC
CLC: TN792
Type: Master's thesis
Year: 2008
Downloads: 39
Quote: 1
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Abstract


As wireless communications, digital high-definition television, multimedia and image processing makes the rapid development of analog circuits and digital circuits as an interface ADC in these areas have been widely used, and integrated circuit technology advances, portable applications requirements make the design of ADC continues toward low-voltage, low-power direction. Among the many ADC structure, pipelined ADC architecture is the most widely used one, it can meet most of the system performance requirements for analog and easy in the modern standard CMOS process to achieve . In this paper, based on the structure of ADC , designed a 1.2V, 10 -bit precision pipelined ADC. This article uses the following technologies to solve low voltage analog circuit design problems , while ensuring a competitive power circuit . 1 In order to solve the short channel transistor intrinsic problem of insufficient gain , using two op-amp , a novel method of frequency compensation to ensure stability at the same frequency amplifier and the amplifier settling time meet the requirements. 2 presents a new bias circuit , the op amp to provide a stable and accurate bias , so that op amp bias and power fluctuations various processes can achieve the large voltage swing. 3 for low supply voltage analog switches are not well on the issue , the input voltage sampling switch using bootstrap technique , while improving this bootstrap switch to fit the bottom plate sampling to ensure that the ADC input at higher frequencies still a very good performance. 4 using RSD digital correction algorithm , which can be used without static power dynamic comparator, reduce the circuit area and power . 5 using op amp sharing technology , which represent the majority of the op amp ADC power consumption almost halved the number . 6 presents a symmetrical layout design methods, making the core part of the circuit layout to achieve completely symmetrical , while in the layout design to ensure the signal flow is reasonable. SMIC 0.13um technology design dirty chip -validated , the chip area of 1.12mm2, the test results show that the ADC has a good static and dynamic performance , and low power consumption to meet the low voltage , portable applications.

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Basic electronic circuits > Digital circuits > Digital-analog , digital to analog conversion circuit
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