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Optimization and Design of High-efficiency Charge Pump for Security SRAM

Author: ChenYue
Tutor: LiuZhengLin
School: Huazhong University of Science and Technology
Course: Software Engineering
Keywords: Security SRAM Data remanence Charge Pump High efficiency Capacitance parasitic parameters
CLC: TN432
Type: Master's thesis
Year: 2009
Downloads: 26
Quote: 1
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Abstract


Due to the feature of high-speed and low power consumption, the SRAM has a wide application. However, as a volatile memory, the SRAM has a data remanence when it’s power off at low temperatures, which brings security risks. To solve this problem, this article has proposed a security SRAM design, which has an integrated self-built power supply module in the general SRAM. When the system detects a power-down, it will automatically rewrite the internal data of the SRAM completely. As the self-built power supply should produce a high-voltage of 7.5 V, we need to design an on-chip charge pump integrated circuit.This paper, in accordance with the security SRAM system, designs an applicable charge pump system, including the charge pump, oscillator and non-overlap clock generator circuit. The structure of the charge pump has both high-drive capability of four-phase dickson charge pump and high voltage gain, high conversion efficiency characteristics of doubler. Considering the security SRAM system, this article determines the stages of charge pump, pump capacitance, output capacitance and clock frequency, shows the working principle and structure characteristics, and analyzes the key performance parameters, such as the output resistance, power consumption and conversion efficiency. To further enhance efficiency, this article gives the optimization program after careful analysis.Finally, this article finishes the simulations of sub-circuits, as well as the charge pump system, and completes the comparison simulation on output voltage and conversion efficiency between the doubler and charge pump of this article. The results show that oscillator provides a frequency of 1.92MHz, for the 46.2% duty cycle square wave output, and charge pump provides an output voltage of 7.465 V. At the same time, charge pump in this article has an output voltage of about 0.12V higher than the doubler, and efficiency is increased by 8%. The Shanghai Hua Hong NEC 0.25μm CMOS process is adopted to implement this design, and then gives the layout of the security SRAM system.

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Microelectronics, integrated circuit (IC) > Semiconductor integrated circuits ( solid state circuits ) > Field-effect type
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