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With the development of microelectronics technology, the design of embedded memories occupy a very important branch in the semiconductor design. As semiconductor technology continues to shrink in proportion to the embedded memory showed higher levels of integration, faster, lower power consumption trends. And is nearly 80% of the digital design silicon area for storage chip, SRAM accounting for a variety of memory total proportion of also rising. SRAM as an important class of semiconductor memory products, has been widely used in the computer, communications, multimedia and other high-speed data exchange system. Therefore, static random access memory depth study has far-reaching significance. SRAM, low power consumption and fast data access characteristics has its strong momentum of development, and a variety of system-on-chip SRAM integrated rapid development. Therefore, in the current situation, under the deep submicron high speed and low power SRAM naturally become one of the hot spots of the research in the field of digital integrated circuits first chapter about the classification of the semiconductor memory, describes the various types characteristics of the memory and works. Chapter II SRAM architecture, detailed description of the structure and design method of the storage array and the peripheral circuits sensitive amplifier, the SRAM decoder circuit and control circuit, and summarizes the advantages and disadvantages are compared. Chapter detailed analysis of the structure and the circuit pattern of the composition of the basic storage unit of the SRAM, illustrates the working principle of the SRAM six units, are selected and determined according to the formulas, and the simulation results of the W / L value of six storage tube, and also analyzes the SRAM memory unit, the static noise margin (SNM), and the power consumption of the SRAM. Six unit based on the design of a high-speed low-power SRAM using TSMC 90nm process technology. And according to the need to design a peripheral circuit of the sense amplifier, decoder, and sense amplifier to do a detailed analysis. Designed the module circuit with specific functions. Finally, the results of the simulation of the entire circuit. Chapter from the optimal angle, on the territory of the overall layout (floor-plan), signal line layout (signal-plan), peripheral circuit layout made specific analysis and design, in order to ensure that the territory quality, the actual territory design maximize the use of the module and traces a symmetrical manner, and the territory of the entire design. In this paper, the design of SRAM capacity of 64K, the readout time of 3ns, write time 1ns, widely used in the secondary cache, ready to tapeout. Some block select signal design, block design storage array, the the classic latch type sense amplifier design method, the decoder uses a pre-decoder technology, six unit territory choreography using 90nm below The most commonly used word line split layout design method, and the whole territory with a reasonable layout placement and routing. These methods can greatly reduce power consumption. Design also designed some peripheral circuits with specific functions, optimization of the entire design.
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