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SoC Test Data Compression Method

Author: ZhuZuoWei
Tutor: YangLianXing
School: Fudan University
Course: Electronics and Communication Engineering
Keywords: SoC Test Data Compression The division of the test source Test compression coding LFSR reseeding
CLC: TN47
Type: Master's thesis
Year: 2010
Downloads: 80
Quote: 0
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Abstract


With IP-based core reuse SoC design method development, greatly simplifying the process of chip design and largely shorten product time to market. But as the number of IP core SoC integration increases, the test application time and test data volume increased dramatically. Meanwhile, the automatic test equipment (ATE) are very expensive, by improving the traditional automatic test equipment to increase its storage capacity and bandwidth way to solve the problem, test costs will rise significantly. Today, SoC test problem has received more and more attention. SoC test data is too large to solve the problems, the most direct and effective way is to test data compression. Furthermore, SoC chip highly integrated so that rapid increases in the complexity of the test, so that the test compression technology also faces enormous challenges. How the SoC chip environment rapid increase in effective compression of the test data volume, to improve the compression efficiency has become a core strategy to overcome the challenge. In this thesis, SoC test data compression methods proposed two new improved scheme, where the main work are: (1) based on the test coding compression techniques, this paper proposes a new coding scheme - Improved Flip continuous sequence Coding (ITCS), the core idea of ??the method is based on the expense of additional expansion in exchange for raw data encoded bit irrelevant bits coding assignment and optimization freedom of choice. Based on the coded data compression method can efficiently compress test data storage, reducing test time is applied. ISCAS-89 benchmarks for the test set circuit experimental results show that the proposed ITCS encoding scheme, which is better than EFDR compression coding, is a very efficient compression method. (2) LFSR reseeding based compression technology, this paper presents the packet-bit fixed-VL-LFSR reseeding techniques to improve test compression coding efficiency. There will be biased by a certain grouping of the input bits are fixed algorithm to achieve the best packet by packet directly to a compatible fixed position to determine a logical value, independent of bits to be encoded, through this operation, the need to replay LFSR kinds of structures to encode data on the location indeed significantly reduced. Finally ISCAS-89 benchmark circuits MinTest test set experiment results show that the coding efficiency than other LFSR reseeding method for SoC test data compression provides an effective solution. This paper presents an improved flip contiguous sequence encoding technology and packet-bit fixed-VL-LFSR reseeding can effectively weaken the expanding scale integrated circuit testing and test speed test hardware made for the demanding requirements of a great extent to save the test equipment cost, has great practical value of the works.

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Microelectronics, integrated circuit (IC) > LSI,ultra LSI
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