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Design of AHB Monitor Based on SHA and AES Algorithms

Author: LuoLiuPing
Tutor: YingJianHua
School: Huazhong University of Science and Technology
Course: Microelectronics and Solid State Electronics
Keywords: Transmission channel security Secure hash function Advanced Encryption Standard Advanced high-performance bus Verilog HDI
CLC: TP309.7
Type: Master's thesis
Year: 2010
Downloads: 12
Quote: 0
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Abstract


Information as an important strategic resource, security has become an important issue of growing concern. Security SoC chip-based information security solutions gradually replacing the traditional build software based on the information security technologies. Security SoC chip is where the information system security control of the core components of its own security is critical. In order to obtain confidential information secure SoC running a variety of means of attack after another, new security measures must therefore be taken to ensure the security of the secure SoC chip. In this paper, the traditional security SoC chip, only the important data encryption and decryption processing, rather than the data transmission channel that effective protection of universal system bus, the researchers designed a way to monitor the the AHB bus behavior of the AHB monitor. The AHB monitor design effectively improves SoC high resistance fault attacks, to prevent security configuration or key program has been tampered run or run the process was deliberately operation. First, several algorithms used AHB monitor principle and improved hardware. In order to meet the requirements of real-time monitoring process, CRC-16 serial implementation mechanism to avoid the tedious process of derivation, the design of a high-speed parallel CRC-16 algorithm; fully SHA-256 algorithm principle based on round by compressing number of operations, the design of the new message extension generation circuit to achieve high data throughput SHA-256 hardware circuit; implementations of the AES-128 algorithm and its key technology research, compare the hardware structure, in order to achieve both ECB, CBC mode using loop iteration structure implementation of AES encryption and decryption, and the same time, in the design of reusable consider the decryption process of computing the same sequence with the encryption process sub. Second, in AHB protocol analysis on the basis of, the three algorithms module has been designed, the design of the core AHB monitor, the premise does not affect the normal operation of the AHB AHB monitor function, can be flexibly configured monitoring algorithm, built-in dedicated DMA can automatically complete the removal of large amounts of data, but also the ability to monitor the bus timeout feature. For the realization of complex the AHB monitor internal hardware resources with AHB monitor configuration non-monitor mode, its built-in SHA-256 and AES-128 algorithm nuclear algorithm modules can be used as ordinary. Using a hardware description language Verilog HDL description of the design completed, the completion of the DC Comprehensive to SMIC 0.13umCMOS technology library, and results show that the design of hardware scale 99.2kgates, and the maximum operating frequency of 142.5MHz, to meet the security SoC system of low costs and increasing operating frequency trends. Again, the AHB monitor hardware design based on, using a variety of EDA tools for simulation and verification, to ensure the correctness of the design from the functional and timing. Finally, summary and outlook of this paper work done, and pointed out areas for improvement in the design, the focus of future research direction.

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CLC: > Industrial Technology > Automation technology,computer technology > Computing technology,computer technology > General issues > Security and confidentiality > Encryption and decryption
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