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With modern communication system, the continuous development of portable consumer electronics and automotive electronics applications, system-level SOC chips to become the mainstream of the development of the market. Research and development of high-performance, low-power, low-cost embedded analog-to-digital converter (ADC) to become today's analog-to-digital converter is an important direction of development. Analog-to-digital converter as peripherals and other analog circuitry and DSP cores integrated on a single chip, so that you can either save the cost of packaging and testing, but also to enhance the reliability of the system. This article summarizes the special requirements of embedded analog-to-digital converter, completed the design of an embedded DSP's 10-bit, 3.3V, 2 MS / s successive approximation ADC. In the system body frame, there is the introduction of a large number of switch circuits, the control of the comparator and a Digital to Analog Converter (DAC), and makes the circuit between the work and power saving mode conversion, thereby reducing unnecessary power consumption. The overall structure of the conventional successive approximation ADC is similar, but inside each module with unique characteristics. Sample-and-hold circuit built-in DAC, save circuit overhead and chips area. Hybrid DAC high charge calibration, the calibration of the low voltage, reducing the use of the passive element, reducing the matching requirements of precision, thereby improving the accuracy of the digital to analog conversion. In order to ensure the speed and linearity of the digital-to-analog conversion, the paper uses two successive comparison of thinking to achieve design: First, one end of the comparator input sample is constant, while the other input is scaled reference voltage ; Second, the comparator, wherein one input terminal of the reference voltage is constant, and the other end is the input sample and the scaled reference voltage is the result of superposition. In order to reduce the requirements of the DAC output voltage of the comparator input range, the use of capacitive the slow pressure technology, boldly final reference voltage of the power supply voltage. Introduced in the design of the high-precision comparator output offset correction (OOS), and the offset correction phase sampling phase merge, reduce the difficulty of timing design. Cadence software on the circuit design, and use Hspice hsim and Matlab circuit system simulation and spectrum analysis, the results show that: the average dynamic power consumption of the ADC module 3.16mW, a maximum sampling rate of 2MHZ, maximum differential non- Linear and integral nonlinearity meet the expected design requirements. In addition, according to the mixed-signal integrated circuit layout design rules, the completion of a successive approximation analog-to-digital converter circuit layout, layout area of ??0.69 mm × 1.23mm. The chip using TSMC 0.18μm, 1.8/3.3V, single poly, six-metal CMOS process, the test results meet the expected design requirements.
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