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Research on the Balance of Power and Precesion of Succsive Approximation A/D Converter Design

Author: GaoXiang
Tutor: YangYinTang
School: Xi'an University of Electronic Science and Technology
Course: Microelectronics and Solid State Electronics
Keywords: Successive Approximation Analog-to-Digital Converter High resolution Low power C-2C structure
CLC: TN792
Type: Master's thesis
Year: 2010
Downloads: 223
Quote: 1
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Abstract


With the development of integrated circuit design coming into the SoC stage, analog, digital and mixed signal modules must be integrated into one chip to form a system .As the interface of analog signal and digital signal analog to digital converters and digital to analog converters are necessary modules in SoC. In the 21 century the development of portable devices and novel technology such as wireless sensor networks, bioinstrumentation are calling for more power-efficent and more capable ICs. Of all kinds of ADC, successive approximation ADC are frequently the architecture of choice in modern SoC design for it’s low power, high resolution performance. The study of SAR ADC design technology also becomes more and more popular in academe.In this thesis, Deeply analysis has been done on the working process of simple and hold circuit. And modeling the non-ideal effect of simple and hold circuit. In connection with charge sharing SAR-ADC, the non-ideal effect caused by element matching was also deeply discussed.A lot of work has been done on analyzing the influence of low supply voltage on some important performance of analog IC, such as signal to noise ratio, working speed, slewing rate and power disspation. In connection with SAR ADC, the influence of low supply voltage on simple and hold circuit was deeply analyzed.Based on the previous analyze, a 12 bits, 1MSPs SAR-ADC with power consumption of less than 500 uW was designed. Simulation has been done based on SMIC 0.18 um CMOS technology.To reach 12bits resolution and less than 500μW power dispation , a new C-2C sub DAC was employed .which was firstly proposed in this thesis. which matching is much easier and take less area than other structures. To improve the ADC’s resolution fully differential comparator and output offset storage technology is also employed .Besides, some new low power capacitor array structures is also introduced.

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Basic electronic circuits > Digital circuits > Digital-analog , digital to analog conversion circuit
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