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An Ultra Low-Voltage, Low-Power PLL

Author: LiangZuo
Tutor: HanYan
School: Zhejiang University
Course: Microelectronics and Solid State Electronics
Keywords: Phase-locked loop Ultra low voltage Low power Fractional-N Adaptive frequency calibration
CLC: TN911.8
Type: Master's thesis
Year: 2012
Downloads: 209
Quote: 2
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Abstract


The explosive development in wireless communications has driven the research and development of low-cost, low-power and smaller RF front-end chips. As a main realization of synthesizers, PLL is a critical device of wireless transceivers. It requires being low-cost and low phase noise. The line-width of CMOS technologies is projected to keep scaling deeper into nanoscale dimensions, so the maximum supply voltage has to be scaled down appropriately. This makes low-voltage circuit research a hot spot. Meanwhile, because of the inherent defects of traditional integer-N PLL, it is now unable to meet increasingly high demand of modern wireless communication systems for frequency switching speed, frequency resolution, noise and other indicators. Therefore, this thesis aims at realizing low phase noise, low voltage (0.8V) fractional-N PLL.At present, the PLL for ultra low voltage application is still in its infancy. There’s still some time before the corresponding products coming out. Research on the fractional-N PLL in our country is prosperity over the past few years, but research on ultra low-voltage is still in its infancy. Thus, the research and development on ultra low-voltage, low-power PLL is extremely important in meeting the needs of market and in the enhancement of IC industry competitiveness of our country.The main work and innovations include:1. Based on the theoretical analysis of PLL system, fractional-N PLL system-level simulation model is established, including linear description model, behavioral model and noise analysis model. Noise transfer characteristics of PLL modules and their contributions to the output phase noise are analyzed, providing a series of guiding principles to optimize the design of phase-locked loops.2. Analyzed the non-ideality of phase frequency detector (dead zone), the non-ideal effects of the charge pump (charging and discharging current mismatch, charge leakage and switching effects), sigma-delta modulator noise shaping characteristics as well as performance indicators and influencing factors of adaptive frequency calibration. Proposed structure to meet the design specifications.3. Based on SMIC 65nm 1P8M CMOS process a 2.4GHz integer-N PLL is implemented. Measurement results have shown that the PLL can work well under 0.8V supply, and the VCOs work under 0.5V supply. The 2.4GHz PLL provide the phase noise of-118.33～-122.34dBc/Hz at 1-MHz offset, and the range of the output frequency is about 2.116～2.419 GHz while dissipating 3.3mW. The settle time is less than 12μs and the spur is less than -69.8dBc. The FOM of the integer-N PLL is -180～-184dB. This design has reached the leading level in China.4. Based on SMIC 65nm 1P8M CMOS process a 6GHz fractional-N PLL is implemented. Measurement results have shown that the PLL can work well under 0.8V supply, and the VCOs work under 0.5V supply. The 6GHz PLL provide the phase noise of-105～-110.5dBc/Hz at 1-MHz offset, and the range of the output frequency is about 5.666～6.21 GHz while dissipating 6.2mW. The settle time is less than 20μs and the spur is less than -53.8dBc. The FOM of the fractional-N PLL is-173～-178dB.5. Besides, a 2.4GHz fractional-N PLL is presented in SMIC 65nm 1P8M CMOS process and the chip is being taped out. It proposed a 24-bits pipeline MASH structure for sigma-delta modulator, and optimized the settle time of AFC. Meanwhile, a parallel to string module is proposed to save the chip area.

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