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Built-In Self Test Research of Digital Circuit

Author: ZhouWen
Tutor: YangChunLing
School: Harbin Institute of Technology
Course: Electrical Engineering
Keywords: ATPG LFSR immune reseeding
CLC: TN79
Type: Master's thesis
Year: 2008
Downloads: 143
Quote: 0
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Abstract


With the continuing development of integrated circuit, lots of DFT(Design OF Testability) measurements have been applied widely to improve test quality and decrease test cost. As one of DFT methods, BIST(Built-in Self Test) can get test vectors in short time, reduce the test complexity and increase fault coverage degree. Furthermore, because it can decrease test time and improve the mensurability and reliability of test system, BIST has become an important method of DFT. Especially in weapon system, it has been applied widely and researched deeply.The main scheme of BIST has been research in the paper, and some new methods have been presented to solve the problems of BIST’application. The main work of this paper has been unfolded as follows:Firstly, a software has been programmed by using certainty test algorithm such as D algorithm and Functional test algorithm to get test vectors for digital circuits based on the research of fault models, fundamental test theory and ATPG(Automatic Test Pattern Generation). The software can get test vectors of combination circuits and sequential circuits.Secondly, the theory of BIST has been researched to get pseudo-random sequence by using LFSR (linear feedback shift register). Then the reseeding method has been presented to cut down the length of test sequence and decrease the test time.Furthermore, a new method of ORA (output response analysis) has been presented in this paper based on the principle of immune system. After using LFSR to compress the output sequences, the sequences can be detected whether there are faults in the circuits or not by uesing immune algorithm. The method presented in this paper can decrease the confusion degree and pick out faults quickly.Finally, the experiments using BIST to test standard circuits shows that test vectors got from certainty test generation algorithm and reseeding method can decrease the test time, reduce the length of test vectors and improve the test performance.

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Basic electronic circuits > Digital circuits
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