Dissertation > Excellent graduate degree dissertation topics show

Design and Implementation of Clock Generator in High Speed ADC

Author: ZhaoHanQiu
Tutor: LiuHongXia；YuXiangHong
School: Xi'an University of Electronic Science and Technology
Course: Software Engineering
Keywords: High speed ADC High-precision Delay lock loop Duty cycle Adjust Divide
CLC: TN792
Type: Master's thesis
Year: 2011
Downloads: 124
Quote: 0
Read: Download Dissertation

Abstract

High-precision clock is the guarantee of the entire chip to work properly in a high-speed ADC to solve chip clock noise , delay and single frequency , you need to be embedded in a high-speed ADC a precision clock generator to meet high-speed ADC timing requirements. To achieve the more stringent requirements for important parameters such as delay and jitter PLL clock generator is a low - cost , high - efficiency programs can produce various frequency required in the system today , but as the clock frequency increases , phase-locked loop design is becoming increasingly difficult , and especially the power problem , especially at high frequencies . Therefore , the clock generator , the proposed new design is very practical value . The issue is to solve this problem , considering the delay , power consumption , area , and other important factors to design one for 500M Hz pipleline ADC clock generator . Process to achieve the design using TSMC 0.18 mm in the delayed phase-locked loop based on a re- design , to reduce the difficulty and power consumption of the clock generator design , design is divided into three modules : clock buffer circuit , clock duty than regulating circuit and clock divider circuit . Clock buffer with differential Bicmos structure to achieve effective clock signal amplification , the clock signal driving ability ; clock duty cycle adjust circuit based on the improved delay PLL circuit divided into frequency synthesizer charge pump detecting circuit , the delay circuit and the shaper , and its function is used to adjust the duty cycle of the external clock to achieve the requirements of the ADC for the clock accuracy ; clock frequency dividing circuit to complete the function of frequency-dividing the clock signal . When the clock generator starts working , the clock signal from the outside , after the clock generator processing , to obtain a stable 50% duty cycle of the clock signal , as a sample and hold circuit control signal and the clock synchronization signals of the ADC module .

Related Dissertations

CLC: > Industrial Technology > Radio electronics, telecommunications technology > Basic electronic circuits > Digital circuits > Digital-analog , digital to analog conversion circuit
© 2012 www.DissertationTopic.Net Mobile