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Sample-and-Hold and MDAC Circuits for Pipeline ADC

Author: SunYuanJie
Tutor: ZhuZhangMing
School: Xi'an University of Electronic Science and Technology
Course: Microelectronics and Solid State Electronics
Keywords: Pipelined ADC High speed Sample and Hold MDAC BiCMOS
CLC: TN792
Type: Master's thesis
Year: 2011
Downloads: 132
Quote: 0
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Abstract


Pipelined analog-to-digital converter (ADC) can be a good compromise between speed, power , area , has become the mainstream of the high-speed high-precision ADC application structure . The sample-and-hold circuit and gain digital-to-analog unit (MDAC) circuit as an important component of the pipeline ADC module , academia and industry and research focus . Papers on pipeline ADC sample-and-hold circuit and MDAC circuit . Shanghai advanced (ASMC) 0.35μm 3.3V/5.0V BiCMOS process , the three first No sample-and-hold operational amplifier (SHA-less) structure , designed for 14 80MHz pipeline ADC integrated sample hold function level MDAC circuit . Papers on the basis of the analysis of the sample-and-hold circuit and the MDAC circuit system structure , completed the the MDAC circuit 's design , and focus on design two BiCMOS fully differential op amp switched capacitor common mode feedback circuit , BiCMOS input buffer and gate voltage bootstrap switches and other circuitry. Simulation results show that the design of two fully differential op amp DC gain of 118dB, unity gain bandwidth of 1.65GHz, phase margin 59 ° . When the sampling frequency is 80MHz, input signal for 8.515625MHz the SNDR of MDAC approximately 73.3dB SFDR approximately 78.2dB effective accuracy of about 12 to meet the system requirements of 14 pipelined ADC MDAC circuit .

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Basic electronic circuits > Digital circuits > Digital-analog , digital to analog conversion circuit
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