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Research on Optimization Model of Nanometer Interconnect with Multiple Target Constraints

Author: HaoBaoTian
Tutor: ZhuZhangMing
School: Xi'an University of Electronic Science and Technology
Course: Microelectronics and Solid State Electronics
Keywords: On-chip interconnect Nanoscale CMOS Power consumption Area Optimization
CLC: TN405.97
Type: Master's thesis
Year: 2011
Downloads: 26
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Abstract

With the continued development of the system - on - chip (SOC) and network - on - chip (NOC) , ULSI frequency and scale of the rise, more and more functional modules integrated on a single chip . This trend is a direct result of the increasing chip size , and also forced the designers to use more interconnection lines to spread the signal . Since designers usually through high - speed interconnect bus structure or point-to-point interconnects to achieve chip subsystems ( such as IP core) and communication between the microprocessor , on-chip interconnect communication has become a the chip performance bottleneck , and become the chip power consumption, important area consumers . Therefore , to solve the on-chip interconnect performance , power consumption , area issues become very important . By simplifying the analysis based on the physical characteristics of the interconnect lines and working mechanism , the introduction of the interconnect electrical parameters of the model , and its simple analysis . Papers to establish a buffer area , interconnect delay , bandwidth and power consumption model , combining buffer insertion and optimize interconnect linewidth technology , an interconnect line optimization model , the model can delay and bandwidth constrained optimization of interconnect power consumption , and inserted into the buffer area . A low - swing techniques , the thesis of the optimization model is a more in-depth study . Subsequent study extended to the on-chip bus, according to the characteristics of the transmission of data on the bus , combined bus Sort and line spacing , design rules and other conditions of the target constraint optimization model of the power consumption of a bus . The experimental results show that this optimization model can effectively reduce interconnect power consumption, and inserted into the buffer area . Finally, we study the on-chip interconnect temperature characteristics consider the interconnect temperature distribution model via effect and the edge of the heat transfer effect , and analysis the impact of the interconnect temperature on interconnect delay and optimize results .

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