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Studies of Single-Event Transient Layout Hardened Techniques and Verification Strategies of Standard Cells

Author: LiuZhen
Tutor: ChenJiHua
School: National University of Defense Science and Technology
Course: Electronic Science and Technology
Keywords: Standard cell Single Event Transient Territory reinforcement Charge collection Simulation and verification
CLC: TN386.1
Type: Master's thesis
Year: 2011
Downloads: 64
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Abstract

With shrinking process geometries, the continuous improvement of the working clock frequency, Single Event Transient (Single Event Transient, SET) gradually over the single event upset (Single Event Upset, SEU), single-particle soft error rate (Soft Error Rate SER the main source of). For anti-radiation of 180nm bulk silicon CMOS process standard cell library, anti SET certain territory reinforcement technology, and simulation and verification method using reinforcement standard cell libraries the excellent irradiation test results, anti-irradiation of high-performance DSP design . The main research content and results, including: a. TCAD three device simulation study well / substrate contact width and well / substrate contact to a different layout structures of the corresponding MOS transistor drain distance MOS gate SET. The results show: For PMOS devices, increasing the width of the well contact and reduce the distance to the drain trap contact can effectively reduce the SET pulse width, Body contact and use P deep well will cause the PMOS bipolar effect becomes stronger; For the NMOS devices, increasing the substrate contact width and reduce the distance of the substrate exposed to the drain SET pulse width can be reduced, but the effect is not obvious, folding gate edition picture method can effectively inhibit the NMOS device SET produces, and N Deep Well SET pulse causes the NMOS device generated wider. Research NMOS ring gate devices the SET effects of reinforcement. This article is designed the same size NMOS ring gate, ring source and ring-drain model for contrast stripe gate device models. TCAD simulation results show that: under the same conditions, the SET pulse width generated in the ring gate devices is smaller than the stripe-shaped gate devices 23%, the SET pulse width generated in the ring the source / drain devices bar gate devices difference; NMOS device source with the PN junction between the P-well is always in a reverse bias state, the source electronic absorption, reducing the number of drain electronic absorption, and inhibit the generation of drain SET. Layout area NMOS the ring gate-structure SET sensitive area is much smaller than the other three structures. Were pointed out combination unit and timing unit anti-SET ability evaluation criteria, and design the corresponding quantitative simulation verification methods. Applied to the entire anti-radiation standard cell library verification method for the quantitative modeling of the input port of the timing unit, greatly improving the efficiency of simulation and verification. As for DICE reinforcement D flip-flop, and pointed out that a single particle bombardment internal storage node when the trigger is read into the data may lead to a decline in the performance of the trigger, and even to generate an error. Text analysis of the internal storage node of the basic the DICE structural trigger sensitivity of this phenomenon, and quantitative study of the trigger reads \impact.

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