Dissertation > Excellent graduate degree dissertation topics show
The Application of Clock Mesh in ASIC Design
Author: HeQi
Tutor: ChenXiaoMing
School: Dalian University of Technology
Course: Microelectronics and Solid State Electronics
Keywords: ASIC Clock grid Clock tree synthesis Clock skew Power consumption
CLC: TN402
Type: Master's thesis
Year: 2011
Downloads: 33
Quote: 0
Read: Download Dissertation
Abstract
|
Since 1947 the first transistor since the emergence of the integrated circuit industry has followed Moore's Law ( Moore 's Law ) . With the continuous improvement of the IC process node , the operating frequency of the chip is getting higher and higher , more and more stringent requirements for clock skew , clock design has become a huge challenge of the designer . According to the ITRS ( International Technology Roadmap for Semiconductors ) , expected in 2009 , the clock frequency of the ASIC ( high-performance ) in 2012 to reach 5.3GHz. In order to close to the zero deviation requirements in the high - speed chip system clock signal assigned to each timing unit , the conventional clock tree synthesis CTS becomes extremely difficult , originally used for the microprocessor clock on the grid structure to be retrieved attention and study. The clock grid structure (Clock Mesh) is a grid shape clock structure , mainly used in the industry on the part of the microprocessor chip ASIC Design ASIC and SoC field no . The clock grid structure on a chip using four sizes obtained chip analysis clock skew (Skew), and compared with the same chip clock tree structure obtained skew conducted , this article data indicate clock grid clock skew more than 50% smaller than the clock tree structure . In addition the overall wiring length of the grid structure of the four sizes and power change , to get the overall wiring length and overall power consumption and the mesh size of the relationship . The data in this description of the overall wiring length will increase with the increase in the size of the grid , the overall power consumption with the increase in the mesh size decreases first and then increases , there will be a minimum value point . If the high-frequency ASIC chip clock grid physical synthesis , which provide a reference for the selection of the best design clock mesh size .
|
Related Dissertations
- Software Approach to Implement Power Optimization in Embedded Handheld Mobile Gis Device,TP311.52
- Research on Low Power Techniques of the Instruction Fetching Unit in Embedded Processors,TP332
- Physical Design of a Chip on NUCSoC,TN47
- A High-Performance Audio ∑△ ADC in 65nm CMOS Process,TN792
- The Research and Design on Wireless HART Adapter,TN915.05
- Low-power、multi-host Interface、multi-layer Design of the LCD Controller,TN873.93
- The Low Power Research of Adaptive Receiver of OFDM Digital Base-band,TN851
- Study on Mobility Management for IPv6-based Wireless Sensor Networks,TP212.9
- Research on Cooperative Transmission Technology in Cognitive Radio Networks,TN925
- Way-predict Based Low Power Cache Design,TP333
- High Efficiency Embedded Processor IP Core,TP332
- A Low Power Power Management System for Passive RFID Tag Chip,TN402
- Heterogeneous data -oriented low-power sensor networks TDMA protocol design and implementation,TP212.9
- Near threshold low-power SRAM study design,TP333
- Locking rail temperature monitoring node sensing unit design and implementation,TP274
- RTL-level and high-performance microprocessor architecture level low power design key technology research,TP332
- Soc - based low - power wireless temperature and humidity acquisition system,TN47
- Research and Design of the Intelligent Dangerous Gas Detector System,TH83
- AES-based security of UHF RFID tag chip research and development,TN402
- For low-power radio-frequency identification tag of a memory circuit,TP333
CLC: > Industrial Technology > Radio electronics, telecommunications technology > Microelectronics, integrated circuit (IC) > General issues > Design
© 2012 www.DissertationTopic.Net Mobile
|