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Study on Interconnect Limits in Deep Sub-Micron IC

Author: WangZiEr
Tutor: MaoJunFa；LiXiaoChun
School: Shanghai Jiaotong University
Course: Electromagnetic Field and Microwave Technology
Keywords: Deep submicron ICs Interconnect Interconnect limit Parameter extraction Delay Bandwidth Optimization
CLC: TN405
Type: Master's thesis
Year: 2009
Downloads: 117
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Abstract

As IC feature sizes shrink , the working frequency increases as well as the expansion of the integration , the integrated circuit interconnect to become the main factor to affect the overall performance of the system . Especially in deep submicron integrated circuits , interconnect line shows the effects of microwave transmission line , interconnect delay over gate delay , interconnect power consumption exceeds the power consumption of the gate . Therefore , the analysis and optimization of the interconnection line to become the key to high - speed integrated circuit design , ultimate performance can be obtained by optimizing the global interconnect lines . This paper studies the performance of global interconnect lines in deep submicron integrated process limit . With process geometries shrink , the effect of showing the limits of global interconnect lines , analyzed the performance of global interconnect optimization problems, the the global interconnection line model , as well as the interconnect and CMOS model system . ( 1 ) This paper first introduces the interconnect concepts from basic theoretical level, the device level and circuit level , analysis of the integrated circuit interconnect limit Facts . ( 2) This article focuses on the global interconnect performance optimization , analysis of the impact of the delay , bandwidth and other performance -based interconnect model (RC and RLC models ) interconnect width and spacing . Discussed whether the buffer into the impact of global interconnect performance optimization results verify effective buffer insertion is a method of reducing global interconnect delay and improve its performance . (3) Finally , the introduction of different interconnect model and use the HSPICE simulation software compares the step response of the global interconnect RC model and RLC models , simulation results verify the conditions of application of RC model , and interconnect selected on the basis of the line model . And interconnecting lines with CMOS cascade circuit was analyzed, and compared the influence of the different interconnection line model and the CMOS device model of the transmission performance . Conclusion: In the design of high-speed integrated circuit , the interconnect line model the impact on performance is higher than the CMOS model .

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