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Parallel Architecture Design and FPGA Verification of Hardware Adaboost Algorithm

Author: JuRan
Tutor: ShiGuoYong
School: Shanghai Jiaotong University
Course: Software Engineering
Keywords: Adaboost Face Detection Assembly line FPGA
CLC: TP338.6
Type: Master's thesis
Year: 2008
Downloads: 161
Quote: 2
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Abstract


Face detection is an important part of the machine vision , widely used in the field of human-computer interaction , video surveillance . How to achieve real - time face detection in embedded systems is a very valuable subject . Cascade Adaboost algorithm - based face detection program faster detection rate , detection rate , the algorithm classifier is divided into a number of stages , only through classifier to determine human face . In the case does not affect the detection accuracy of the fewer number of feature classifiers on the front, and quick to exclude most of the non-face regions , can significantly improve detection speed. However , the algorithm needs to access data volume and high computational complexity , simply pure software solutions , it is difficult to achieve real-time detection requirements . Program implemented in hardware can take full advantage of the hardware parallel processing features , pipeline technology , can greatly improve the detection speed , to achieve real-time detection requirements , at the same time save a lot of CPU and memory resources of embedded systems . This paper analyzes several existing the Adaboost algorithm hardware architecture , consuming logic resources , detect speed , memory access efficiency analysis , design a new array unit structure , and take full advantage of the parallel processing capabilities of the hardware in one clock calculate the number of rectangular gray and cycle . The array unit structure was seized window fixed detection window size ( 20 x 20) , to change the size of the subject image scanning strategy , can effectively reduce the the detection unit cost of hardware resources . Array architecture design with a high degree of parallelism , only need to increase the the set MUX parallel system can be increased by 1 ( the degree of parallelism is the n system can be calculated in each clock cycle n rectangular gradation ) . The design uses a the Xilinx Spartan3A DSP FPGA verification , with the video input and output modules , in case the system clock is 50MHz , real-time detection of VGA resolution (640 × 480) images .

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CLC: > Industrial Technology > Automation technology,computer technology > Computing technology,computer technology > Electronic digital computer (not a continuous role in computer ) > A variety of electronic digital computer > Parallel computer
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