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The Research and Design of Sample and Hold Circuit in Pipelined ADC

Author: HongYi
Tutor: ZouXueCheng
School: Huazhong University of Science and Technology
Course: Microelectronics and Solid State Electronics
Keywords: Sample and Hold Circuit Pipeline Analog-to-Digital Converter Bootstrapped Sampling Switch Setting Time
CLC: TN792
Type: Master's thesis
Year: 2008
Downloads: 139
Quote: 0
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Abstract


In recent years, analog-to-digital converters have gained great development in process, architecture and performance. Sample and hold circuit is developing towards high speed and high precision which is in the front of the ADC. The setting error and setting speed are the most important parameters of the Sample-and-Hold circuit which affects the resolution and speed of the whole pipelined ADC directly. Therefore the design of sample and hold circuit become the most important cell in pipelined ADC. An 8 bit 25 MHz pipelined ADC S/H circuit is introduced in this thesis.The relevant techniques about the design of Sample-and-Hold circuit in pipelined ADC are discussed in this thesis. Firstly, Starting from basic principles of Sample and hold circuit, we analysis the sample and hold modes in details. Secondly we analysis the Non-ideal factors impacting the Sample-and-hold circuit in every mode fully and deeply. Factors effecting analog switch performance in the holding mode, such as charge injection, switch clock feed-through, Nonlinear of switch resistance and so on are analyzed as well. We study Mathematical model of set-up time of operational amplifier in details while at the same time, comparisons of Various-structure operational amplifier performance are made. Then Modeling in Matlab is used to analysis the whole system. And for situation of Non-ideal circumstances, we propose the improvement for every factor effecting analog switch performance, and use Optimum Designing for operational amplifier with the generalized geometric method.The sample and hold circuit is simulated by Cadence with standard 0.18μm CMOS process model. The simulation shows that with 12.5 MHz input sine-waves which is at 25 MHz sampling rate, gain error is less than 117.49μV, slewing settling time reached 7.76 ns, SNR for the output DFT is 57.27 dB while Pipelined ADC sampling rate optimized to be 8 bit 25 MHz Pipelined ADC. Sample and hold circuit designed in this thesis can be applied to related ADC.

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Basic electronic circuits > Digital circuits > Digital-analog , digital to analog conversion circuit
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