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Study of Deep Submicron Strained Silicon Devices by Simulation

Author: ShiZuo
Tutor: GuXiaoFeng
School: Jiangnan University
Course: Microelectronics and Solid State Electronics
Keywords: Strained silicon Stress CMOS Omega FinFET Simulation TCAD Sentaurus
CLC: TP391.9
Type: Master's thesis
Year: 2009
Downloads: 183
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Abstract

With the rapid development of the integrated circuit (IC) technology, the feature size of transistors has entered the deep sub-micron, even ultra-deep submicron (nanometer) level. Continue to follow the scaling method to improve the current mainstream silicon CMOS device performance is limited by the more and more physical, process. Can keep Moore's Law indicates that the pace of development in order to make the IC, it is necessary to study the development compatible with silicon technology, new materials, new performance and new structure, which has become the consensus of academia and industry. In recent years, strained silicon technology and novel FinFET structure concern for excellence in improving the performance of CMOS devices. For example, a typical CMOS strained silicon device through the drain region of the PMOS source growth SiGe S / D and the compression stress in the surface of the device is deposited SiN liner to introduce channel compressive stress, by control strain to improve the hole mobility, to improve the performance of the device ; stress memory technology (SMT) can be used in the NMOS and depositing SiN stress liner the introducing channel tensile stress, through the control strain to improve the electron mobility, to improve the device performance. Optimize the process design of deep submicron and nanometer semiconductor devices, the structure parameters of stress on the device performance has important scientific significance and practical value. However, the (super) micro-stress localized in the deep submicron semiconductor structure, the precise measurement of the strain usually requires the help of complex micro-structure analysis, measurement means. Currently, nano-strain stress distribution in silicon devices, as well as the impact of stress on device performance from experimental studies yet carried out in the country. This paper attempts to use two-dimensional simulation study the TCAD tools on some of the new structure, and to explore the feasibility of introducing stress engineering in CMOS devices and device performance; addition, a three-dimensional simulation study of the new Omega FinFET structure. In practical work, the first use Sentaurus representative strained silicon CMOS devices, and get the key electrical characteristics (e.g., Ion / Ioff), and the actually measured data of the device can be produced in the similar process under good agreement, to verify the model used and the correctness of the technical route. Secondly, the design of the stress introduced in various combinations, and the stress distribution and the relationship of the device parameters. The simulation results show that the introduction of stress engineering can significantly improve the device threshold voltage change characteristics, switching current characteristics and subthreshold electrical behavior, thereby significantly improving the performance of CMOS devices. Depth study on this basis, the PMOS channel stresses and device performance is affected by the influence of the Ge mole fraction parameters, as well as NMOS channel strain by the intrinsic stress of the SiN cushion layer, the influence of the film thickness and device performance. Finally, using the Sentaurus three-dimensional simulation of the electrical properties of Omega FinFET reasonable critical electrical parameters; further verify the correctness of the basis of simulation methods to study the electrical properties of the Omega FinFET. The results for the design of the new strained silicon devices produced measurements provide a useful reference.

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