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Analog - to - digital converter (ADC) as an interface circuit , widely used in audio , video , communications , earthquake prediction , and medical electronic systems . With the processing capabilities of these systems and gradually increase processing speed , accuracy and speed performance associated with the analog-to-digital converter of increases. Oversampling Sigma-Delta ADC is a new type of analog-to-digital converter is different from the traditional Nyquist ADC sampling and noise shaping two key technologies , most driven to quantization noise outside the signal band , and then use the digital low-pass filter to filter out -of-band noise , the conversion accuracy has been significantly improved , and is very suitable to be applied in areas such as audio and digital telephone . This paper focuses on a specific project depth study on the part of a suitable for VoIP chip , high-precision Sigma-Delta ADC modulator , designed with a chopper stabilized the second the monocyclic Sigma - Delta modulator . Modulator using the switched capacitor circuit to achieve; oversampling rate of 128 , the signal bandwidth is 24KHz ; quantization for a quantization . The article first analyzes the works of the Sigma-Delta modulator , single-loop , cascade , and the structure of a number of quantitative modulator focus on concrete analysis of the actual circuit performance of a variety of non - ideality factor modulator impact. Including these non - ideality factor of operational amplifier finite DC gain , the limited unity gain bandwidth and limited slew rate , circuit noise and clock jitter . Then , in the Matlab environment of the second-order Sigma-Delta modulator behavioral simulation to determine the key indicators required by the circuit design . On this basis , each unit circuit of the Sigma-Delta modulator is a transistor-level design , including a switch capacitor integrator , a comparator , a DAC, and the non-overlapping clock signal generator circuit and the like . Finally, Cadence Spectre circuit simulation . This design uses CSMC 0.5μm CMOS process . The simulation results show that , in the case of the power supply voltage of 5 V, the sampling frequency of 6.144 MHz , Sigma-Delta modulator design available 81.6dB dynamic range , the conversion accuracy of 13.26 , reached the design requirements .
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