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Implementation and Research of High-Performance FFT Algorithm Based on FPGA

Author: XuNa
Tutor: YangDingCai
School: Yanshan University
Course: Circuits and Systems
Keywords: Fast Fourier Transform Field Programmable Gate Array Butterfly processor Pipelined architecture Block floating structure
CLC: TP332
Type: Master's thesis
Year: 2009
Downloads: 547
Quote: 1
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Abstract


Fast Fourier Transform (FFT) as the time domain and frequency domain conversion of the basic operations , and is a necessary prerequisite for the digital spectrum analysis . More difficult to meet real-time high-speed processing , application specific integrated circuit (ASIC) , and programmable logic devices ( field programmable gate array FPGA ) came into the traditional FFT use software or DSP . Speed ??ASIC more dominant chip area will rapidly expand However, with the increase of the number of points , which means the cost of the improvement . Internal FPGA contains a hardware multiplier, a lot of memory and programmable I / O, is very suitable for the realization of the FFT processor , and the relative ASIC , low cost , and can be repeated programming , ease of debugging , and also more competitive market . This paper presents the design and implementation of the 1024-point FFT processor in the FPGA . ( 1) The method uses a decimation-in-time (DIT) -4 algorithm and a 5 -stage pipeline structure and core unit butterfly processors and pipelined architecture to improve the design , so that it saves about 75% of the hardware area also greatly improve the speed of operations , so as to achieve a system of high-speed real-time requirements . ( 2 ) design of the built-in dual-port RAM to store data , and control is simple and fast ; twiddle factor ROM storage and lookup table to fetch , to save time . ( 3) To avoid data overflow using block floating structure to represent the data , this is a good compromise of fixed-point and floating-point numbers , and save a lot of device resources . ( 4 ) Finally, to be verified by Matlab simulation results of the hardware implementation of the FFT algorithm , in order to prove the correctness of the method proposed in this paper . The test results show that the method at the same time ensure the accuracy of the computation and implementation complexity , improve the data clock frequency of the processor and the processing speed to achieve the desired objectives .

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CLC: > Industrial Technology > Automation technology,computer technology > Computing technology,computer technology > Electronic digital computer (not a continuous role in computer ) > Arithmetic unit and the controller (CPU)
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