Dissertation > Excellent graduate degree dissertation topics show

Design of 65nm SRAM

Author: ZhangQiang
Tutor: WuXiaoBo；ZhaoMengLian
School: Zhejiang University
Course: Circuits and Systems
Keywords: SRAM MUX clock generator decoder
CLC: TP333
Type: Master's thesis
Year: 2010
Downloads: 221
Quote: 0
Read: Download Dissertation

Abstract


With the development of semiconductor technology, the feature size of transistor is shrinking down to tens of nanometer. As results, its speed continuosly increases. Howerer, process fluctuations also increases with the shrikage and brings more challenges to SRAM design.Aimed at increasing speed, reducing power and area, suppressing process fluctuations, this thesis designed a 1024x32 SRAM based on the research of 65nm SRAM architecture. The layout is 0.0376 mm2, the average current is 4.3mA and the CLK to Q is 0.548ns in post simulation. The main content is as follows:1. Through research on SRAM MUX, the performances of one-tier and two-tier architecture and the corresponding single and dual structures were analyzed theoretically, from which it was derived that the larger the characteristic number of sense amplifier, the better the two-tier architecture in comparison with one-tier one. The optimum two-tier architecture is achieved when the characteristic numbers of the two-stage decoder are close. The optimum two-tier architecture could reduce up to 33.6% of read access time compared with the conventional one-tier one.2. SRAM clock generator was analyzed and researched in details. The performances of two mainstream discharge circuits was analyzed and compared based on probability. And the the results were verified by one hundred thousand Monte Carlo simulations. Based on it, the better discharge circuit was chosen to build the clock generator. The clock generator is capable of well coordinating the different part of SRAM. Besides, it can dynamically adjust the access speed for manufactured chip.3. Through analyzing and researching the SRAM decoder circuit, the important factors in SRAM design were derived and the design methodology for low power and fast access decoder was introduced. Meanwhile, the application of logical effort theory to decoder design was discussed and expounded. Finally, the circuit model of asymmetric logical gates was built and its application to decoder design was introduced based on analysis of its advantages.

Related Dissertations

  1. The Optimization of AVS Video Decoder on the PC Platform and Improvement of Field Decoding,TN919.81
  2. Development of Pxibus High Performance Digital I/O Module,TP274
  3. Stability of the SRAM Cells for Deep Sub-micron Technologies,TP333
  4. Design of a 2.5GHz PLL Clock Generator,TN911.8
  5. Aircraft Condition Monitoring System Research and Improvement,TP277
  6. Research on Signal Detectionalgorithm for MIMO Systems,TN919.3
  7. Research on OCDMA/WDM Hybrid Optical Network System,TN929.11
  8. Design and Development of NVR Software Platform Based on ONVIF Protocol,TP311.52
  9. Optimization and Implementation of MPEG-4 AAC Audio Decoder,TN912.3
  10. Design and Implementation of Parallel LTE Turbo Decoder,TN929.5
  11. Software Design of Multi-Channel H.264 Decoder Base on DM6467 DSP Processor,TN919.81
  12. Convolutional code decoding algorithm and its FPGA implementation,TN791
  13. Embedded video decoder motion compensation process data layout optimization,TN919.81
  14. Embedded SRAM under 65nm process technology research and implementation,TP333
  15. SRAM -based FPGA fault propagation characteristics of single-particle testing method,V467
  16. LDPC code decoding algorithm research and implementation,TN911.22
  17. Implementation of H.264 Decoder Based on the FFmpeg,TN919.81
  18. Research and Realization of LDPC Decoder in High Speed Data Transmission,TN911.22
  19. Design of the Memory System for Digital Signal Processor,TP333
  20. Reconfigurable Design of LDPC Decoder,TN911.22
  21. Reed-Solomon decoder implementation study,TN762

CLC: > Industrial Technology > Automation technology,computer technology > Computing technology,computer technology > Electronic digital computer (not a continuous role in computer ) > Memory
© 2012 www.DissertationTopic.Net  Mobile