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Ethernet Controller Physical Layer Clock Recovery Circuit Design

Author: LiLiang
Tutor: ZhangTao
School: Wuhan University of Science and Technology
Course: Circuits and Systems
Keywords: The clock recovery circuit Phase interpolation Phase-locked loop Voltage Controlled Oscillator
CLC: TP273
Type: Master's thesis
Year: 2011
Downloads: 41
Quote: 0
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Abstract


With the rapid development of the information age , the rapid development of network , wired network is an essential part of information transmission carrier . The rapid growth of network bandwidth not only meet the speed requirements , but also to provide a stable and reliable transmission carrier . The the network reliability mainly by the data transfer process , the frame dropping rate, and data error correction capability , bit error rate , and other indicators to be measured. In order to ensure that data can be received during reception reliable data , and improve data transfer rates , a high-performance clock / data recovery circuit is we need to find a function module . In this paper, a PI structure - based clock recovery circuit structure, which for 10M/100Mbps Ethernet physical layer chip , to provide a reliable system clock chip . The clock recovery circuit of the main module comprises the frequency discriminator phase detector, a charge pump, a low pass filter , VCO , and 10/11 dual divider . The PLL circuit is designed in this paper at a supply voltage of 2.5V , the output of the center frequency of 250MHz , and having the ability to quickly lock . The VCO in the off-center frequency 600KHz at the phase noise of -108dBc/Hz . This design mainly includes the design of high speed PFD circuit using a master-slave D-type flip-flop , the flip-flop , the ability to have a high - speed flip , able to work in a high operating frequency ; designed switching current steering charge pump , the the charge pump has a rapid charge- discharge characteristics ; designed a current hunger Difference oscillator , the oscillator uses the 11 -stage differential delay unit , the output 11 of different phases of 250MHz clock frequency is used to recover the data of the post-stage circuit ; design a 10 / 11 dual modulus divider , 250MHz clock frequency of the VCO output divided by 10 for the PFD phase . The simulation of the present paper is based the Spectre software platform completed , the completion the Ethernet controller physical layer clock recovery circuit of the system simulation , to verify the feasibility of the clock recovery circuit . Determined through the analysis of simulation results , the performance of the clock recovery circuit to meet Ethernet requirements .

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