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Gain unit based on the high - speed low data maintain power consumption eDRAM design

Author: ChengKuan
Tutor: LinYinYin
School: Fudan University
Course: Microelectronics and Solid State Electronics
Keywords: Dynamic Random Access Memory Embedded Logic process Gain unit High-speed read and write A compact charge transfer refresh
CLC: TP333
Type: Master's thesis
Year: 2011
Downloads: 8
Quote: 0
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Abstract


This paper first describes the course of development of the dynamic random access memory , followed by evaluation of embedded memory . Drawn in the analysis and comparison of a variety of dynamic random access memory unit for the purpose of embedded applications , a logic process and unit readout speed optimization , data retention time improved 2T gain cell . Peripheral circuit design for this unit array architecture and completed basic read and write operations . Keep the power requirements for embedded memory, high speed and low data , the use of high-speed read and write preamplifier literacy programs and compact charge transfer refresh program to design a test chip . The simulation results show that : the refresh mode and traditional 6ns clock cycle , the memory write operation 3ns, a 23% reduction compared with the traditional scheme ; data access time of 1.8ns, a 15% reduction compared with the traditional program ; program compared to the sense amplifier power consumption reduced by 58% , the refresh time reduced by 43 % .

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CLC: > Industrial Technology > Automation technology,computer technology > Computing technology,computer technology > Electronic digital computer (not a continuous role in computer ) > Memory
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