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For low-power radio-frequency identification tag of a memory circuit

Author: BiZhongYu
Tutor: ZuoZuo
School: Fudan University
Course: Microelectronics and Solid State Electronics
Keywords: Resistance change memory EEPROM Radio frequency identification Tag chip UHF Low power consumption Low Voltage Low cost High capacity Standard CMOS process Regulation loop Sensitive amplifier
CLC: TP333
Type: Master's thesis
Year: 2011
Downloads: 133
Quote: 0
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Abstract


Radio Frequency Identification (RFID: Radio Frequency Idendification) is a radio frequency signal used to achieve non-contact transmission of information and identification technologies. As the information storage medium, the embedded non-volatile memory (Embedded Non-Volatile Memory) RFID tag is an indispensable component. With the popularity of RFID technology and in-depth, networking, aviation industry and other emerging application areas of the label of the non-volatile memory made large-capacity, low-power, low-cost integrated requirements. This thesis is based on the application requirements, applicable to RFID tags embedded non-volatile memory design carried out a lot of research, and select resistive memory (RRAM) and electrically erasable read-only memory (EEPROM) for the chip. Firstly, the system analysis of the UHF passive tag system performance requirements of the memory circuit, gives a suitable UHF RFID tags for the non-volatile memory should have the basic performance indicators. Followed by a detailed analysis of this paper RRAM with EEPROM storage mechanism, cell structure and application characteristics, and other embedded non-volatile memory with a comprehensive analysis and comparison, the system analyzes the RRAM application with the EEPROM in the current context of their own advantages disadvantages and difficulties for the existing design gives the corresponding solutions. RRAM memory, this paper presents the design and applies 2T2R (dual control tube - double resistive memory cell) storage structure of the differential sense amplifier with the band peak current cancellation feature of the regulator loop readout in achieving low power consumption while eliminating the charge pump start large currents. In this paper, while the storage array, the bit line path, charge pump, write feedback control circuit and other key module for a detailed analysis and optimization. On this basis, the paper on the SMIC 0.13μm standard process design and implementation of the world's first 64-Kbit RRAM memory with passive UHF tags, test results show that the memory chip 640 Kb / s data rate reading power consumption of 2.2μA, at 5 KB / s write data rate of the write power consumption is 18.5μA, memory circuit a total area of ??0.39mm2. EEPROM memory, this paper for large-capacity EEPROM, designed to improve the EEPROM readout circuit, the SMIC 0.18μm EEPROM technology to achieve a low-voltage, low-power readout. Tests show that the improved readout circuit to the following work at 0.7V, and the lowest power consumption is less than 21μA.

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CLC: > Industrial Technology > Automation technology,computer technology > Computing technology,computer technology > Electronic digital computer (not a continuous role in computer ) > Memory
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