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Suitable for multi-mode wireless communication system can be configured pipelined ADC Research and Design

Author: ChenQiHui
Tutor: HongZhiLiang
School: Fudan University
Course: Microelectronics and Solid State Electronics
Keywords: Analog-to-Digital Converter Assembly line Sample and Hold Op amp sharing Reference voltage buffer Gate voltage bootstrap Step by step simulation
CLC: TN792
Type: Master's thesis
Year: 2011
Downloads: 80
Quote: 0
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Abstract


With the development of wireless communication technology, flexible and configurable wireless transceiver design technique is currently a hot research. One of the key challenges to achieve this technology in the analog-to-digital converter technology. For compatibility with multiple wireless communication standards such as WCDMA, TD-SCDMA and GSM protocol, analog-to-digital converter in the wireless transceiver system must achieve accuracy or speed can be configured to meet the performance requirements for each standard, while consuming minimum. In addition, the new generation of wireless transceiver system is often integrated analog, digital, and RF circuits on the same silicon to reduce costs. The same power supply voltage used by the wafer is decreased with the reduction in size of integrated circuit technology, which is conducive to the reduction of power consumption of digital circuitry, but also reduces the dynamic range of the signal, and limits the accuracy of the analog-to-digital converter. Therefore, under the deep sub-micron and nanometer process system integration, low-voltage design of the analog-to-digital converter is also challenging. Paper, pipelined ADC structure trade-off between accuracy, speed, area and power, and is conducive to the performance can be configured. Through the adjustment of the current size of the key modules, analog-to-digital converter in each mode to achieve higher energy efficiency. Obtain a larger signal swing at low supply voltages, the analog-to-digital converter with two Cascode compensation op-amp configuration. The main innovation lies in: 1) omitted the input of the sample and hold circuit, and by improving the first-level sub-analog-to-digital converter sampling network to match the sampling circuit of the first stage residue amplifier; 2) In addition to the first level of In addition, between adjacent stages using double-folding differential input pair of the operational amplifier sharing, saving the isolation switch in the traditional op amp sharing technology; 3) the use of a low-power chip reference voltage buffer for the analog-to-digital The converter provides high-precision differential reference voltage. The pipelined analog-to-digital converter with the 0.13um layer of polycrystalline eight metal CMOS process, the chip core area of ??1.40mm2. Chip silicon proven, the test results show that: in each mode have reached more than 10.5 accuracy, maximum SFDR and SNDR can reach 90dB and 69.2dB the average FOM value of approximately 0.46pJ/conv-step. The 5MHz sinusoidal input signal and the sampling frequency of 30.1MHz, differential nonlinearity and integral nonlinearity of -0.30 to 0.21LSB and -0.57 to 1.15LSB. This design has been applied to the monolithic multi-mode wireless communication receiver.

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Basic electronic circuits > Digital circuits > Digital-analog , digital to analog conversion circuit
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