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Pipelined analog-to-digital converter design

Author: WuHaiJun
Tutor: LiuNuo；CaoXianGuo
School: University of Electronic Science and Technology
Course: Microelectronics and Solid State Electronics
Keywords: Analog-to-Digital Converter Assembly line Operational amplifier Territory
CLC: TN792
Type: Master's thesis
Year: 2008
Downloads: 204
Quote: 0
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Abstract


An analog-to-digital converter (ADC) is an interface circuit, the analog signal to digital signal conversion in modern signal processing systems are widely used. Pipelined ADC has the advantages of high-speed, high-precision because of its own structure, its low power consumption, and therefore concern. Based on 1.5 / stage pipelined ADC works and structural studies, the establishment of a model and the results of analysis of the key modules, and design a 10-bit, 60 MHz, 1.5 / pipeline analog-to-digital The converter modules territory. This work includes the following four parts: 1, proceed from the principle of pipelined analog-to-digital converter, 1.5 / stage pipeline ADC principles and digital correction techniques. Using Simulink tools to analyze the results of operational amplifiers and comparators error. Different circuit design of the structure and performance of the pipelined ADC technology, a detailed study of the technology used in the pipelined ADC as well as raise the level of craft and design new design techniques. Based on SMIC 0.18μm CMOS mixed signal process, design and simulation of the circuit in the 10-bit 60 MHz pipelined ADC. The design module: (1) the bandgap reference source; (2) the sample-and-hold circuit; (3) Multiplying DACs; (4) operational amplifier; (5) comparator; (6) bootstrap switch. Conducted a systematic analysis of the sample and hold circuit and operational amplifier, the noise characteristics of the multiplying digital-to-analog converter and the on-resistance of the switch. Sub-ADC designed, non-overlapping clock circuit delay array and digital correction circuit module. Bandgap reference source in TT process under temperature changes from -40 ° to 125 ° changes in the reference voltage 1.2mV, 5.3mV change in FF process. Operational amplifier bandwidth up to 400 MHz, the phase margin of 70 °. A BC logical structure of the module in the digital correction circuit composed of a full adder correction logic compared with the advantages of a simple structure and a small tube. 3, system simulation, and results show that the input ramp signal, almost no missing codes; enter 2 MHz sine signal sampling frequency of 60 MHz, the conversion result is correct, the analysis results show that the spurious-free dynamic range of 60dB , static power consumption is about 200mW. Finally, cooperation in the design part of the territory of the circuit, bandgap reference, bootstrap switch, non-overlapping clock circuit and triggers. Layout module above, need to pay attention to match the devices and parasitics. Analysis of the MOS transistor, capacitor and resistor layout and connection so as to achieve a match and how to avoid antenna effect. The territory of each module in the entire chip layout design, analog and digital blocks should be separated. At the same time should be in accordance with the direction of the signal flow layout.

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Basic electronic circuits > Digital circuits > Digital-analog , digital to analog conversion circuit
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