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Research and Design of SEU immunity of SRAM -based FPGA test system

Author: HuangJinJie
Tutor: YuJun
School: Fudan University
Course: Microelectronics and Solid State Electronics
Keywords: Based on static random access memory structure Field Programmable Gate Array Single Event Effects Single-particle reinforcement Triple modular redundancy Readback reconfiguration Error injection
CLC: TN791
Type: Master's thesis
Year: 2011
Downloads: 126
Quote: 0
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Abstract


Compared to other types of chips used in a radiation environment, based the SRAM structure FPGAs with high logic density, low cost and may be amended after launch and mission updates a unique advantage, but there are more susceptible to single-event upset effects. As our country in such technology is still in the exploratory stage, how to SRAM-based FPGA SEU reinforcement and effective testing and evaluation become an urgent problem to be solved. To get rid of the kinds of situation, so that the SRAM-based FGPA get better in a radiation environment in China, the phenomenon of single particle in the radiation environment for Single Event Effects generated by the chip research and analysis, while the multi- kind of try to design a single particle of SRAM-based FPGAs reinforcement, and the reinforcing effect of the single-particle test system. Use the system the XCV300 chip of Xilinx's conduct a error injection simulation test, under the specific fluence rate single-particle irradiation measured similar circuit flip cross section is estimated to produce functional error-sectional test results are compared with the irradiation test, an evaluation of the test system. The main duties include: study concluded SRAM-based FPGA SEU (Single Event Upset, SEU) effect mechanism, as well as the SEU Hardened and tested principles and methods; design a single FPGA chip particle reinforcement, reinforcement both single-particle radiation trial and error injection simulation and test systems. Including PC control client software, system testing PCB and test circuit structure; using self-designed test system to be measured FPGA error injection simulation, with the radiation test test results are compared and analyzed. The paper designed test system can be more convenient remote control and circuit configuration updates, which can reduce the complexity of the test, with a focus on improving the simulation injection system. SRAM-based FPGA configuration bit-flip probability is independent of the specific circuit structure, but only with the injection of particle parameters (fluence rate, angle of incidence of the incident area, etc.). In view of this, it is possible for a specific injection particle simulation can be simulated SRAM-based FPGA circuit in the the irradiation test case of the general situation, can provide very useful reference design for the circuit in a radiation environment.

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Basic electronic circuits > Digital circuits > Logic circuits
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